AT89C51ED2-RDTUM Atmel, AT89C51ED2-RDTUM Datasheet - Page 96

IC 8051 MCU FLASH 64K 64VQFP

AT89C51ED2-RDTUM

Manufacturer Part Number
AT89C51ED2-RDTUM
Description
IC 8051 MCU FLASH 64K 64VQFP
Manufacturer
Atmel
Series
89Cr
Datasheet

Specifications of AT89C51ED2-RDTUM

Core Processor
8051
Core Size
8-Bit
Speed
60MHz
Connectivity
SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
50
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
UART, SPI
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
50
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
Cpu Family
AT89
Device Core
8051
Device Core Size
8b
Frequency (max)
40MHz
Total Internal Ram Size
2KB
# I/os (max)
50
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
VQFP
For Use With
AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT89C51ED2-RDTUM
Manufacturer:
ATMEL
Quantity:
19 090
Part Number:
AT89C51ED2-RDTUM
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
AT89C51ED2-RDTUM
Manufacturer:
MICROCHIP/微芯
Quantity:
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96
AT89C51RD2/ED2
After programming the part by ISP, the BSB must be cleared (00h) in order to allow the applica-
tion to boot at 0000h.
The content of the Software Security Byte (SSB) is described in Table 24-4 and Table 24-5.
To assure code protection from a parallel access, the HSB must also be at the required level.
Table 24-4.
The two lock bits provide different levels of protection for the on-chip code and data, when pro-
grammed as shown in Table 24-5.
Mnemonic
Number
1-0
BSB
SSB
Bit
7
6
5
4
3
2
7
-
Mnemonic
Definition
Boot Status Byte
Software Security Byte
Copy of the Manufacturer Code
Copy of the Device ID #1: Family Code
Copy of the Device ID #2: Memories Size and
Type
Copy of the Device ID #3: Name and Revision
Software Security Byte
LB1-0
Bit
6
-
-
-
-
-
-
-
Description
Reserved
Do not clear this bit.
Reserved
Do not clear this bit.
Reserved
Do not clear this bit.
Reserved
Do not clear this bit.
Reserved
Do not clear this bit.
Reserved
Do not clear this bit.
User Memory Lock Bits
See Table 24-5
5
-
4
-
3
-
Default value
0FFh
ECh
FFh
D7h
EFh
58h
2
-
Atmel
C51 X2, Electrically Erasable
AT89C51RD2/ED2 64KB
AT89C51RD2/ED2 64KB,
Revision 0
LB1
Description
1
4235K–8051–05/08
LB0
0

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