LPC1751FBD80,551 NXP Semiconductors, LPC1751FBD80,551 Datasheet - Page 55

• Manufacturer Part Number: LPC1751FBD80,551
• Description: IC ARM CORTEX MCU 32K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1751FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: CAN, I2C, SPI, UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 3
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• Cpu Family: LPC17xx
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 100MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 52
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.4/2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: LQFP
• Package: 80LQFP
• Family Name: LPC17xx
• Maximum Speed: 100 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4788; 935287916551

NXP Semiconductors
Table 15.
C
[1]
LPC1759_58_56_54_52_51
Product data sheet
Symbol
t
t
t
V
t
t
t
t
t
t
r
f
FRFM
FEOPT
FDEOP
JR1
JR2
EOPR1
EOPR2
Fig 20. Differential data-to-EOP transition skew and EOP width
L
CRS
= 50 pF; R
Characterized but not implemented as production test. Guaranteed by design.
T
PERIOD
differential
data lines
Dynamic characteristics: USB pins (full-speed)
pu
= 1.5 k
11.8 USB interface
Parameter
rise time
fall time
differential rise and fall time
matching
output signal crossover voltage
source SE0 interval of EOP
source jitter for differential transition
to SE0 transition
receiver jitter to next transition
receiver jitter for paired transitions
EOP width at receiver
EOP width at receiver
Ω
on D+ to V
n × T
differential data to
crossover point
DD(3V3)
SE0/EOP skew
PERIOD
All information provided in this document is subject to legal disclaimers.
; 3.0 V
+ t
FDEOP
Rev. 6.01 — 11 March 2011
≤
V
DD(3V3)
Conditions
10 % to 90 %
10 % to 90 %
see
see
10 % to 90 %
must reject as
EOP; see
Figure 20
must accept as
EOP; see
Figure 20
t
r
/ t
≤
Figure 20
Figure 20
f
3.6 V.
crossover point
LPC1759/58/56/54/52/51
extended
[1]
[1]
32-bit ARM Cortex-M3 microcontroller
Min
8.5
7.7
-
1.3
160
−2
−18.5
−9
40
82
source EOP width: t
receiver EOP width: t
Typ
-
-
-
-
-
-
-
-
-
-
© NXP B.V. 2011. All rights reserved.
Max
13.8
13.7
109
2.0
175
+5
+18.5
+9
-
-
FEOPT
002aab561
EOPR1
, t
EOPR2
55 of 74
Unit
ns
ns
%
V
ns
ns
ns
ns
ns
ns