LPC1751FBD80,551 NXP Semiconductors, LPC1751FBD80,551 Datasheet - Page 56

• Manufacturer Part Number: LPC1751FBD80,551
• Description: IC ARM CORTEX MCU 32K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1751FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: CAN, I2C, SPI, UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 3
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• Cpu Family: LPC17xx
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 100MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 52
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.4/2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: LQFP
• Package: 80LQFP
• Family Name: LPC17xx
• Maximum Speed: 100 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4788; 935287916551

NXP Semiconductors
LPC1759_58_56_54_52_51
Product data sheet
11.9 SPI
Table 16.
T
[1]
[2]
Symbol
T
T
t
t
SPI master
t
t
t
t
SPI slave
t
t
t
t
SPICLKH
SPICLKL
SPIDSU
SPIDH
SPIQV
SPIOH
SPIDSU
SPIDH
SPIQV
SPIOH
amb
Fig 21. SPI master timing (CPHA = 1)
cy(PCLK)
SPICYC
T
processor clock CCLK.
Timing parameters are measured with respect to the 50 % edge of the clock PCLK and the 10 % (90 %)
edge of the data signal (MOSI or MISO).
=
SPICYC
−
40
°
= (T
Dynamic characteristics of SPI pins
C to +85
SCK (CPOL = 0)
SCK (CPOL = 1)
Parameter
PCLK cycle time
SPI cycle time
SPICLK HIGH time
SPICLK LOW time
SPI data set-up time
SPI data hold time
SPI data output valid time
SPI output data hold time
SPI data set-up time
SPI data hold time
SPI data output valid time
SPI output data hold time
cy(PCLK)
All information provided in this document is subject to legal disclaimers.
MOSI
MISO
°
× n) ± 0.5 %, n is the SPI clock divider value (n ≥ 8); PCLK is derived from the
C.
Rev. 6.01 — 11 March 2011
DATA VALID
[1]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
T
DATA VALID
SPICYC
LPC1759/58/56/54/52/51
t
SPIQV
Min
10
79.6
0.485
0
2
2
2
0
2
2
2
×
×
×
×
×
×
T
T
T
T
T
T
cy(PCLK)
cy(PCLK)
cy(PCLK)
cy(PCLK)
cy(PCLK)
cy(PCLK)
×
32-bit ARM Cortex-M3 microcontroller
T
t
t
SPICYC
SPICLKH
SPIDSU
− 5
+ 30
+ 5
+ 5
+ 35
+ 15
DATA VALID
DATA VALID
t
SPICLKL
t
SPIDH
Typ
-
-
-
-
-
-
-
-
-
-
-
-
Max
-
-
-
0.515
-
-
-
-
-
-
-
-
t
002aad986
© NXP B.V. 2011. All rights reserved.
SPIOH
×
T
SPICYC
56 of 74
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns