ST72F260G1M6 STMicroelectronics, ST72F260G1M6 Datasheet - Page 96

• Manufacturer Part Number: ST72F260G1M6
• Description: MCU 8BIT 4K FLASH ICP 28SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F260G1M6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Data Converters: A/D 6x10b
• Processor Series: ST72F2x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7F264-IND/USB, ST72F34X-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6-ch x 10-bit
• Controller Family/series: ST7
• No. Of I/o's: 22
• Ram Memory Size: 256Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• For Use With: 497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-4840

ST72260Gx, ST72262Gx, ST72264Gx
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
11.5.5 Low Power Modes
11.5.6 Interrupts
The SCI interrupt events are connected to the
same interrupt vector.
These events generate an interrupt if the corre-
sponding Enable Control Bit is set and the inter-
96/172
Mode
WAIT
HALT
In Halt mode, the SCI stops transmit-
ting/receiving until Halt mode is exit-
ed.
Description
No effect on SCI.
SCI interrupts cause the device to exit
from Wait mode.
SCI registers are frozen.
rupt mask in the CC register is reset (RIM instruc-
tion).
Transmit Data Register
Empty
Transmission Com-
plete
Received Data Ready
to be Read
Overrun Error Detected
Idle Line Detected
Parity Error
Interrupt Event
Event
TDRE
RDRF
Flag
IDLE
OR
TC
PE
Control
Enable
TCIE
ILIE
Bit
RIE
TIE
PIE
from
Wait
Exit
Yes
Yes
Yes
Yes
Yes
Yes
from
Halt
Exit
No
No
No
No
No
No