EZ80F93AZ020SG Zilog, EZ80F93AZ020SG Datasheet - Page 111
![IC ACCLAIM MCU 64KB 100LQFP](/photos/6/76/67664/269-100-lqfp_sml.jpg)
EZ80F93AZ020SG
Manufacturer Part Number
EZ80F93AZ020SG
Description
IC ACCLAIM MCU 64KB 100LQFP
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F93AZ020SG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
100-LQFP
Processor Series
EZ80F93x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F920200ZCOG
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-3874
EZ80F93AZ020SG
EZ80F93AZ020SG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Universal Asynchronous Receiver/Trans-
mitter
PS015313-0508
The UART module implements all of the logic required to support several asynchronous
communications protocols. The module also implements two separate 16-byte-deep
FIFOs for both transmission and reception. A block diagram of the UART is displayed in
Figure
The UART module provides the following asynchronous communication protocol-related
features and functions:
•
•
•
•
•
•
•
5-, 6-, 7-, 8- or 9-bit data transmission
Even/odd, space/mark, or no parity bit generation and detection
Start and stop bit generation and detection
Supports up to two stop bits
Line break detection and generation
Receiver overrun and framing errors detection
Logic and associated I/O to provide modem handshake capability
Interrupt Signal
System Clock
I/O Address
25.
Data
Figure 25.UART Block Diagram
Transmit
Receive
Modem
Control
Buffer
Buffer
Logic
Universal Asynchronous Receiver/Transmitter
RxD0/RxD1
TxD0/TxD1
CTS0/CTS1
RTS0/RTS1
DSR0/DSR1
DTR0/DTR1
DCD0/DCD1
RI0/RI1
Product Specification
eZ80F92/eZ80F93
104
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