EZ80F93AZ020SG Zilog, EZ80F93AZ020SG Datasheet - Page 252
![IC ACCLAIM MCU 64KB 100LQFP](/photos/6/76/67664/269-100-lqfp_sml.jpg)
EZ80F93AZ020SG
Manufacturer Part Number
EZ80F93AZ020SG
Description
IC ACCLAIM MCU 64KB 100LQFP
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F93AZ020SG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
100-LQFP
Processor Series
EZ80F93x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F920200ZCOG
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-3874
EZ80F93AZ020SG
EZ80F93AZ020SG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Clocking Overview 141
Complex triggers 187
CONTINUOUS mode 76, 78, 79, 80, 81, 82, 84, 85
CPHA 132
CPHA bit 133
CPOL 132
CPOL bit 133
CPU system clock cycle 54
CS0 9, 21, 48, 49, 50, 51
CS1 9, 21, 48, 49, 50, 51
CS2 9, 21, 48, 50, 51
CS3 9, 21, 48, 50, 51
CTS 119, 122
CTS0 14, 128
CTS1 16
Customer Information 253
D
DATA bus 60
Data Bus 10
data bus 52, 53, 55, 56, 57, 64, 70, 90, 169, 179, 185
Data Carrier Detect 14, 17, 122
Data Set Ready 14, 16, 122
Data Terminal Ready 14, 16, 119
Data Transfer Procedure with SPI configured as a
Slave 135
Data Transfer Procedure with SPI Configured as the
Master 135
data transfer, SPI 138
Data Validity 142
DC Characteristics 223
DCD 119, 122
DCD0 14, 128
DCD1 17
DCTS 122
DDCD 122
DDSR 122
divisor count 110, 135
DSR 119, 122
DSR0 14, 128
DSR1 16
DTACK 64
DTR 119, 122
PS015313-0508
P R E L I M I N A R Y
DTR0 14, 128
DTR1 16
E
edge-selectable interrupts 43
edge-triggered interrupt input 128
edge-triggered interrupt mode 41, 43
Edge-Triggered Interrupts 42
EI, Op Code Map 213
Electrical Characteristics 222
ENAB 157
Enabling and Disabling the WDT 73
ENAB—see Bus Enable bit 155
Endec 129
endec 125, 128
endec—see Infrared Encoder/Decoder 37, 124, 128
Erase operations 193, 194
Event Counter 80
External Bus Acknowledge Timing 238
external bus request 52, 165, 169
External I/O Chip Selects 25
External I/O Read Timing 233
External I/O Write Timing 234
External Memory Read Timing 230
External Memory Write Timing 231
external pull-down resistor 40
External System Clock Driver (PHI) Timing 238
eZ80 bus mode 66, 70
eZ80 CPU 11, 35, 52, 56, 57, 64, 171, 187
eZ80 CPU Core 31
eZ80 CPU Instruction Set 208
eZ80 Product ID Low and High Byte Registers 182
eZ80 Product ID Revision Register 183
eZ80 system clock cycle 53, 54, 57, 60
eZ80 Webserver-i 208
eZ80F92 3, 72, 171, 183
eZ80F92 device 1, 4, 5, 10, 25, 35, 39, 45, 46, 48,
50, 66, 76, 80, 108, 110, 153, 163, 164, 165, 167,
175, 176, 180, 181, 185, 219, 223, 224, 229, 238
eZ80F92 processor 2
D R A F T
Product Specification
Index
244
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