EZ80F93AZ020SG Zilog, EZ80F93AZ020SG Datasheet - Page 161
![IC ACCLAIM MCU 64KB 100LQFP](/photos/6/76/67664/269-100-lqfp_sml.jpg)
EZ80F93AZ020SG
Manufacturer Part Number
EZ80F93AZ020SG
Description
IC ACCLAIM MCU 64KB 100LQFP
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F93AZ020SG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
100-LQFP
Processor Series
EZ80F93x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F920200ZCOG
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-3874
EZ80F93AZ020SG
EZ80F93AZ020SG
Available stocks
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Part Number
Manufacturer
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PS015313-0508
Table 84. I
I
The I2C_XSAR register is used in conjunction with the I2C_SAR register to provide
10-bit addressing of the I
8 bits of the 10-bit slave address. The full 10-bit address is supplied by {I2C_SAR[2:1],
I2C_XSAR[7:0]}.
When the register receives an address starting with
the I
after receiving the I2C_XSAR byte (the device does not generate an interrupt at this
point). After the next byte of the address (I2C_XSAR) is received, the I
interrupt and goes into SLAVE mode. Then I2C_SAR[2:1] are used as the upper 2 bits for
the 10-bit extended address. The full 10-bit address is supplied by {I2C_SAR[2:1],
I2C_XSAR[7:0]}. See
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:1]
SLA
0
GCE
2
C Extended Slave Address Register
2
C recognizes that a 10-bit slave addressing mode is selected. The I
2
C Slave Address Registers(I2C_SAR = 00C8h)
Value Description
00h–
7Fh
0
1
Table 85
2
C when in SLAVE mode. The I2C_SAR value forms the lower
R/W
7-bit slave address or upper 2 bits,I2C_SAR[2:1], of address
when operating in 10-bit mode.
I
I
7
0
2
2
C not enabled to recognize the General Call Address.
C enabled to recognize the General Call Address.
on page 155.
R/W
6
0
R/W
5
0
R/W
F7h
4
0
to
F0h
R/W
3
0
(I2C_SAR[7:3] = 11110b),
Product Specification
R/W
2
0
I2C Serial I/O Interface
2
2
C generates an
C sends an ACK
R/W
1
0
R/W
0
0
154
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