EZ80F93AZ020SG Zilog, EZ80F93AZ020SG Datasheet - Page 208
![IC ACCLAIM MCU 64KB 100LQFP](/photos/6/76/67664/269-100-lqfp_sml.jpg)
EZ80F93AZ020SG
Manufacturer Part Number
EZ80F93AZ020SG
Description
IC ACCLAIM MCU 64KB 100LQFP
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F93AZ020SG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
100-LQFP
Processor Series
EZ80F93x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F920200ZCOG
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-3874
EZ80F93AZ020SG
EZ80F93AZ020SG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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PS015313-0508
Flash Frequency Divider Register
The 8-bit frequency divider allows programming to Flash over a range of system clock
frequencies. Flash can programmed with system clock frequencies ranging from 154 kHz
through 50 MHz. The Flash controller requires an input clock with a period that falls
within the range of 5.1 µs to 6.5 µs. The period of the Flash controller clock is set through
the Flash Frequency Divider register. Writes to this register are allowed only after it is
unlocked via the FLASH_KEY register. The Frequency Divider register value required
versus system clock frequency is listed in
the ranges shown in this table are not supported.
Table 117. Flash Frequency Divider Values
Table 118. Flash Frequency Divider Register; (FLASH_FDIV = 00F9h)
System Clock Frequency
154–196 kHz
308–392 kHz
462–588 kHz
616 kHz–50 MHz
Note: *The CEILING function rounds fractional values up to the next whole
Bit
Reset
CPU Access
Note: R/W = Read/Write, R = Read Only. *Key sequence required to enable Writes
Bit
Position
[7:0]
FLASH_FDIV
number, for example, CEILING(3.01) is 4.
Value Description
01h–
FFh
R/W*
Divider value for generating the required 5.1–6.5 μs Flash
controller clock period.
7
0
R/W*
Flash Frequency Divider Value
CEILING [System Clock Frequency
1
2
3
(MHz) x 5.1 (μs)]*
6
0
Table
R/W*
5
0
117. System clock frequencies outside of
R/W*
4
0
R/W*
3
0
Product Specification
R/W*
2
0
eZ80F92/eZ80F93
R/W*
1
0
Flash Memory
R/W
0
1
201
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