EZ80F93AZ020SG Zilog, EZ80F93AZ020SG Datasheet - Page 166
![IC ACCLAIM MCU 64KB 100LQFP](/photos/6/76/67664/269-100-lqfp_sml.jpg)
EZ80F93AZ020SG
Manufacturer Part Number
EZ80F93AZ020SG
Description
IC ACCLAIM MCU 64KB 100LQFP
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F93AZ020SG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
100-LQFP
Processor Series
EZ80F93x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F920200ZCOG
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-3874
EZ80F93AZ020SG
EZ80F93AZ020SG
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PS015313-0508
Note:
Table 89. I
If an illegal condition occurs on the I
00h
IFLG bit cleared. The I
on the I
Code
40h
48h
50h
58h
60h
68h
70h
78h
80h
88h
90h
98h
A0h
A8h
B0h
B8h
C0h
C8h
D0h
D8h
F8h
). To recover from this state, the STP bit in the I2C_CTL register must be set and the
2
The STP and STA bits may be set to 1 at the same time to recover from the bus
error. The I
C bus.
2
Status
Address and Read bit transmitted, ACK received
Address and Read bit transmitted, ACK not received
Data byte received in MASTER mode, ACK transmitted
Data byte received in MASTER mode, NACK transmitted
Slave address and Write bit received, ACK transmitted
Arbitration lost in address as master, slave address and Write bit received,
ACK transmitted
General Call address received, ACK transmitted
Arbitration lost in address as master, General Call address received, ACK
transmitted
Data byte received after slave address received, ACK transmitted
Data byte received after slave address received, NACK transmitted
Data byte received after General Call received, ACK transmitted
Data byte received after General Call received, NACK transmitted
STOP or repeated START condition received in SLAVE mode
Slave address and Read bit received, ACK transmitted
Arbitration lost in address as master, slave address and Read bit received,
ACK transmitted
Data byte transmitted in SLAVE mode, ACK received
Data byte transmitted in SLAVE mode, ACK not received
Last byte transmitted in SLAVE mode, ACK received
Second Address byte and Write bit transmitted, ACK received
Second Address byte and Write bit transmitted, ACK not received
No relevant status information, IFLG = 0
C Status Codes (Continued)
2
C then sends a START condition.
2
C then returns to the idle state. No STOP condition is transmitted
2
C bus, the bus error state is entered (status code
Product Specification
I2C Serial I/O Interface
159
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