EZ80F93AZ020SG Zilog, EZ80F93AZ020SG Datasheet - Page 49
![IC ACCLAIM MCU 64KB 100LQFP](/photos/6/76/67664/269-100-lqfp_sml.jpg)
EZ80F93AZ020SG
Manufacturer Part Number
EZ80F93AZ020SG
Description
IC ACCLAIM MCU 64KB 100LQFP
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F93AZ020SG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
100-LQFP
Processor Series
EZ80F93x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F920200ZCOG
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-3874
EZ80F93AZ020SG
EZ80F93AZ020SG
Available stocks
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Part Number
Manufacturer
Quantity
Price
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PS015313-0508
GPIO Interrupts
Each port pin can be used as an interrupt source. Interrupts can be either level- or edge-
triggered.
Level-Triggered Interrupts
When the port is configured for level-triggered interrupts, the corresponding port pin is
tristated. An interrupt request is generated when the level at the pin is the same as the level
stored in the Port x Data register. The port pin value is sampled by the system clock. The
input pin must be held at the selected interrupt level for a minimum of 2 consecutive clock
cycles to initiate an interrupt. The interrupt request remains active as long as this condition
is maintained at the external source.
For example, if PD3 is programmed for low-level interrupt and the pin is forced Low for 2
consecutive clock cycles, an interrupt request signal is generated from that port pin and
sent to the CPU. The interrupt request signal remains active until the external device
driving PD3 forces the pin High.
Edge-Triggered Interrupts
When the port is configured for edge-triggered interrupts, the corresponding port pin is
tristated. If the pin receives the correct edge from an external device, the port pin generates
System Clock
Data Bus
GPIO Register
Data (Output)
D
System Clock
Figure 5. GPIO Port Pin Block Diagram
Q
Mode 1
Mode 4
Mode 1
Mode 3
GPIO Register
Data (Input)
Q
D
Q
General-Purpose Input/Output
Product Specification
D
GND
eZ80F92/eZ80F93
V
DD
Port
Pin
42
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