C8051F321-GM Silicon Laboratories Inc, C8051F321-GM Datasheet - Page 187

• Manufacturer Part Number: C8051F321-GM
• Description: IC 8051 MCU 16K FLASH 28MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F321-GM

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 21
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: I2C/SMBus/SPI/UART/USB
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F320DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 13-ch x 10-bit or 17-ch x 10-bit
• No. Of I/o's: 21
• Ram Memory Size: 1280Byte
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1480 - DAUGHTER CARD TOOLSTCK C8051F321770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1449 - ADAPTER PROGRAM TOOLSTICK F321336-1260 - DEV KIT FOR C8051F320/F321
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1261

16.5. SMBus Transfer Modes
The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be operating
in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or Slave Receiver. The
SMBus interface enters Master Mode any time a START is generated, and remains in Master Mode until it loses an
arbitration or generates a STOP. An SMBus interrupt is generated at the end of all SMBus byte frames; however, note
that the interrupt is generated before the ACK cycle when operating as a receiver, and after the ACK cycle when
operating as a transmitter.
16.5.1. Master Transmitter Mode
Serial data is transmitted on SDA while the serial clock is output on SCL. The SMBus interface generates the START
condition and transmits the first byte containing the address of the target slave and the data direction bit. In this case
the data direction bit (R/W) will be logic 0 (WRITE). The master then transmits one or more bytes of serial data.
After each byte is transmitted, an acknowledge bit is generated by the slave. The transfer is ended when the STO bit
is set and a STOP is generated. Note that the interface will switch to Master Receiver Mode if SMB0DAT is not writ-
ten following a Master Transmitter interrupt. Figure 16.8 shows a typical Master Transmitter sequence. Two transmit
data bytes are shown, though any number of bytes may be transmitted. Notice that the ‘data byte transferred’ inter-
rupts occur after the ACK cycle in this mode.
Interrupt
S
Figure 16.8. Typical Master Transmitter Sequence
Received by SMBus
Interface
Transmitted by
SMBus Interface
SLA
W
Interrupt
A
Data Byte
Rev. 1.1
Interrupt
A
S = START
P = STOP
A = ACK
W = WRITE
SLA = Slave Address
Data Byte
Interrupt
A
C8051F320/1
P
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