C8051F321-GM Silicon Laboratories Inc, C8051F321-GM Datasheet - Page 74
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C8051F321-GM
Manufacturer Part Number
C8051F321-GM
Description
IC 8051 MCU 16K FLASH 28MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F32xr
Datasheets
1.C8051F320-TB.pdf
(250 pages)
2.C8051F321-GMR.pdf
(2 pages)
3.C8051F321-GM.pdf
(256 pages)
Specifications of C8051F321-GM
Program Memory Type
FLASH
Program Memory Size
16KB (16K x 8)
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
21
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2.25 KB
Interface Type
I2C/SMBus/SPI/UART/USB
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
21
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F320DK
Minimum Operating Temperature
- 40 C
On-chip Adc
13-ch x 10-bit or 17-ch x 10-bit
No. Of I/o's
21
Ram Memory Size
1280Byte
Cpu Speed
25MHz
No. Of Timers
4
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1480 - DAUGHTER CARD TOOLSTCK C8051F321770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1449 - ADAPTER PROGRAM TOOLSTICK F321336-1260 - DEV KIT FOR C8051F320/F321
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1261
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F321-GM
Manufacturer:
SiliconL
Quantity:
4 364
Part Number:
C8051F321-GM
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Part Number:
C8051F321-GMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
C8051F320/1
Performance
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051
architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to exe-
cute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51 core executes 70% of its instruc-
tions in one or two system clock cycles, with no instructions taking more than eight system clock cycles.
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has a total of
109 instructions. The table below shows the total number of instructions that for execution time.
Programming and Debugging Support
In-system programming of the FLASH program memory and communication with on-chip debug support logic is
accomplished via the Silicon Labs 2-Wire Development Interface (C2). Note that the re-programmable FLASH can
also be read and changed a single byte at a time by the application software using the MOVC and MOVX instruc-
tions. This feature allows program memory to be used for non-volatile data storage as well as updating program code
under software control.
The on-chip debug support logic facilitates full speed in-circuit debugging, allowing the setting of hardware break-
points, starting, stopping and single stepping through program execution (including interrupt service routines), exam-
ination of the program's call stack, and reading/writing the contents of registers and memory. This method of on-chip
debugging is completely non-intrusive, requiring no RAM, Stack, timers, or other on-chip resources. C2 details can
be found in
The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs provides an
integrated development environment (IDE) including editor, macro assembler, debugger and programmer. The IDE's
debugger and programmer interface to the CIP-51 via the C2 interface to provide fast and efficient in-system device
programming and debugging. Third party macro assemblers and C compilers are also available.
74
Number of Instructions
Clocks to Execute
Section “21. C2 Interface” on page
26
1
50
2
253.
2/3
Rev. 1.1
5
14
3
3/4
7
4
3
4/5
1
5
2
8
1