HD64F3687GFPV Renesas Electronics America, HD64F3687GFPV Datasheet - Page 185
![IC H8 MCU FLASH 56K 64LQFP](/photos/12/19/121969/hd64f3687gfpv_sml.jpg)
HD64F3687GFPV
Manufacturer Part Number
HD64F3687GFPV
Description
IC H8 MCU FLASH 56K 64LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Specifications of HD64F3687GFPV
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
56KB (56K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
64-LQFP
Package
64LQFP
Family Name
H8
Maximum Speed
20 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16|32 Bit
Number Of Programmable I/os
45
Interface Type
I2C/SCI
On-chip Adc
8-chx10-bit
Number Of Timers
3
For Use With
R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F3687GFPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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10.4.3
When the seconds, minutes, hours, or day-of-week datum is updated while time data is being read,
the data obtained may not be correct, and so the time data must be read again. Figure 10.4 shows
an example in which correct data is not obtained. In this example, since only RSECDR is read
after data update, about 1-minute inconsistency occurs.
To avoid reading in this timing, the following processing must be performed.
1. Check the setting of the BSY bit, and when the BSY bit changes from 1 to 0, read from the
2. Making use of interrupts, read from the second, minute, hour, and day-of week registers after
3. Read from the second, minute, hour, and day-of week registers twice in a row, and if there is
second, minute, hour, and day-of-week registers. When about 62.5 ms is passed after the BSY
bit is set to 1, the registers are updated, and the BSY bit is cleared to 0.
the IRRTA flag in IRR1 is set to 1 and the BSY bit is confirmed to be 0.
no change in the read data, the read data is used.
Data Reading Procedure
Figure 10.4 Example: Reading of Inaccurate Time Data
Before update
After update
BSY bit = 0
BSY bit -> 1 (under data update)
BSY bit -> 0
(1) Day-of-week data register read
(2) Hour data register read
(3) Minute data register read
(4) Second data register read
RWKDR = H'03, RHDDR = H'13, RMINDR = H'47, RSECDR = H'00
RWKDR = H'03, RHDDR = H'13, RMINDR = H'46, RSECDR = H'59
H'00
H'03
H'13
H'46
Rev.5.00 Nov. 02, 2005 Page 151 of 500
Section 10 Realtime Clock (RTC)
REJ09B0027-0500
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