HD64F3687GFPV Renesas Electronics America, HD64F3687GFPV Datasheet - Page 303

IC H8 MCU FLASH 56K 64LQFP

HD64F3687GFPV

Manufacturer Part Number
HD64F3687GFPV
Description
IC H8 MCU FLASH 56K 64LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheets

Specifications of HD64F3687GFPV

Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
56KB (56K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
64-LQFP
Package
64LQFP
Family Name
H8
Maximum Speed
20 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16|32 Bit
Number Of Programmable I/os
45
Interface Type
I2C/SCI
On-chip Adc
8-chx10-bit
Number Of Timers
3
For Use With
R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3687GFPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F3687GFPV
Manufacturer:
RENESAS
Quantity:
1 000
16.3.8
BRR is an 8-bit register that adjusts the bit rate. The initial value of BRR is H'FF. Table 16.3
shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 of
SMR in asynchronous mode. Table 16.4 shows the maximum bit rate for each frequency in
asynchronous mode. The values shown in both tables 16.3 and 16.4 are values in active (high-
speed) mode. Table 16.5 shows the relationship between the N setting in BRR and the n setting in
bits CKS1 and CKS0 of SMR in clocked synchronous mode. The values shown in table 16.5 are
values in active (high-speed) mode. The N setting in BRR and error for other operating
frequencies and bit rates can be obtained by the following formulas:
[Asynchronous Mode]
[Clocked Synchronous Mode]
Legend B: Bit rate (bit/s)
N: BRR setting for baud rate generator (0 N 255)
n: CSK1 and CSK0 settings in SMR (0 n 3)
Bit Rate Register (BRR)
: Operating frequency (MHz)
Error (%) =
N =
N =
(N + 1)
64
8
2
2
2n–1
2n–1
B
10
64
B
6
Section 16 Serial Communication Interface 3 (SCI3)
B
2
10
10
2n–1
6
6
– 1
– 1
Rev.5.00 Nov. 02, 2005 Page 269 of 500
– 1
100
REJ09B0027-0500

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