HD64F3687GFPV Renesas Electronics America, HD64F3687GFPV Datasheet - Page 378

• Manufacturer Part Number: HD64F3687GFPV
• Description: IC H8 MCU FLASH 56K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3687GFPV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 56KB (56K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• Package: 64LQFP
• Family Name: H8
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 45
• Interface Type: I2C/SCI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• For Use With: R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 18 A/D Converter
18.4.3
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (t
starts conversion. Figure 18.2 shows the A/D conversion timing. Table 18.3 shows the A/D
conversion time.
As indicated in figure 18.2, the A/D conversion time includes t
length of t
time therefore varies within the ranges indicated in table 18.3.
In scan mode, the values given in table 18.3 apply to the first conversion time. In the second and
subsequent conversions, the conversion time is 128 states (fixed) when CKS = 0 and 66 states
(fixed) when CKS = 1.
Rev.5.00 Nov. 02, 2005 Page 344 of 500
REJ09B0027-0500
Input Sampling and A/D Conversion Time
D
varies depending on the timing of the write access to ADCSR. The total conversion
Address
Write signal
Input sampling
timing
ADF
[Legend]
(1) :
(2) :
t
t
t
D
SPL
CONV
:
:
:
A/D conversion start delay time
Input sampling time
A/D conversion time
ADCSR write cycle
ADCSR address
Figure 18.2 A/D Conversion Timing
(1)
(2)
t
D
t
SPL
D
) has passed after the ADST bit is set to 1, then
t
CONV
D
and the input sampling time. The