HD64F3687GFPV Renesas Electronics America, HD64F3687GFPV Datasheet - Page 386
![IC H8 MCU FLASH 56K 64LQFP](/photos/12/19/121969/hd64f3687gfpv_sml.jpg)
HD64F3687GFPV
Manufacturer Part Number
HD64F3687GFPV
Description
IC H8 MCU FLASH 56K 64LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Specifications of HD64F3687GFPV
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
56KB (56K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
64-LQFP
Package
64LQFP
Family Name
H8
Maximum Speed
20 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16|32 Bit
Number Of Programmable I/os
45
Interface Type
I2C/SCI
On-chip Adc
8-chx10-bit
Number Of Timers
3
For Use With
R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F3687GFPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 19 EEPROM
19.4
19.4.1
The HD64N3687G has a multi-chip structure with two internal chips of the HD64F3687G (F-
ZTAT™ version) and 512-byte EEPROM. The HD6483687G has a multi-chip structure with two
internal chips of the HD6433687G (mask-ROM version) and 512-byte EEPROM.
The EEPROM interface is the I
communication with the external devices connected to the I
19.4.2
The I
specific for the EEPROM are the following two.
1. The EEPROM address is configured of two bytes, the write data is transferred in the order of
2. The write data is transmitted from the MSB side.
The bus format and bus timing of the EEPROM are shown in figure 19.2.
19.4.3
A high-to-low transition of the SDA input with the SCL input high is needed to generate the start
condition for starting read, write operation.
Rev.5.00 Nov. 02, 2005 Page 352 of 500
REJ09B0027-0500
SDA
SCL
[Legend]
R/W: R/W code (0 is for a write and 1 is for a read),
ACK: acknowledge
upper address and lower address from each MSB side.
condition
Start
2
C bus format and the I
Operation
EEPROM Interface
Bus Format and Timing
Start Condition
1
2
Slave address
3
4
Figure 19.2 EEPROM Bus Format and Bus Timing
5
6
2
C bus timing follow section 17.4.1, I
7
2
C bus interface. This I
R/W ACK
8
9
Upper memory
A15
1
address
A8
8
ACK
9
A7
lower memory
1
2
C bus is open to the outside, so the
address
2
C bus can be made.
A0
8
ACK
9
2
C Bus Format. The bus formats
D7
1
Data
D0
8
ACK
9
D7
1
Data
D0
8
ACK
9
conditon
Stop
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