HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 212

IC H8/SLP MCU FLASH 80QFP

HD64F38024DV

Manufacturer Part Number
HD64F38024DV
Description
IC H8/SLP MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300L SLPr
Datasheets

Specifications of HD64F38024DV

Core Processor
H8/300L
Core Size
8-Bit
Speed
10MHz
Connectivity
SCI
Peripherals
LCD, PWM, WDT
Number Of I /o
51
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F38024DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Notes: 1. Generated by the compiler when a C++ program has a global class object.
198
(c) ROM, RAM allocation
(d) Allocation of initialized data areas
Used Runtime Library Name
(e) Example of memory allocation and address specification at link time
When writing a program to ROM, whether sections are allocated to RAM or to ROM is
determined by whether there are initial values and whether write operations are enabled.
When writing the sections of a C/C++ program to ROM, sections are allocated to ROM or
to RAM as follows.
Sections which have initial values and can be altered on program execution, such as
initialized data areas, are placed in ROM at link time and copied to RAM at the start of
program execution. Hence the rom option of the optimizing linkage editor must be used to
reserve the duplicate memory area both in ROM and in RAM. For an example of this, refer
to "(e) Example of memory allocation and address specification at link time" below. Initial
settings for sections to be copied from ROM to RAM are explained in section 9.2.2 (2),
Initial settings (PowerON_Reset).
When creating an absolute load module, addresses are specified per allocated area for each
section using an optimizing linkage editor option or a subcommand. Below, examples of
static memory allocation and of address specification at link time are explained.
Figure 9.4 shows an example of allocation of a static memory area in H8S/2600 advanced
mode.
2. Generated by the compiler when a C++ program contains virtual function declarations.
$MULL$3
Program area (section P)
Constant areas (sections C, $ABS8C, $ABS16C)
Uninitialized data areas (sections B, $ABS8B, $ABS16B)
Initialized data areas (sections D, $ABS8D, $ABS16D)
(see (d) below)
Function address area (section $INDIRECT, $EXINDIRECT)
Initialized data section address area (section C$DSEC)
Uninitialized data section address area (section C$BSEC)
Initial processing data area*
Virtual function table area*
2
1
(section C$VTBL)
(section C$INIT)
: Runtime routine
ROM
ROM
ROM
ROM
ROM
ROM
ROM
RAM
ROM, RAM

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