HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 63

• Manufacturer Part Number: HD64F38024DV
• Description: IC H8/SLP MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD64F38024DV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

ENAble_register: Preferential Allocation of register Storage Class Variables
C/C++ <Other> [Miscellaneous options :][Enable register declaration]
STRIct_ansi: ANSI Conformance
C/C++ <Other> [Miscellaneous options :][Obey ansi specifications more strictly]
Remarks
Output of the messages which were changed to the information-level can be suppressed by the
nomessage option.
An error number which is not defined is ignored.
When this option is specified more than once, all the specifications are valid. If a number is
specified more than once, the last specification is valid.
Format
ENAble_register
Description
Preferentially allocates the variables with register storage class specification to registers.
Remarks
If a variable cannot be allocated to a register, message
allocated to "variable name" in "function name"
that this message will not be output if a parameter is not allocated to a register. This option is
valid only when the CPU type is H8SX or H8S(without legacy=v4 option).
Format
STRIct_ansi
Description
Conforms to the ANSI standard for the following processing:
Remarks
When this option is specified, the operation results may be different from Ver.6.0 compiler or
earlier.
This option is valid only when the CPU type is H8SX or H8S(without legacy=v4 option).
Associative rule of floating-point operations
C0101 (I) Register is not
will be output. Note, however,
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