MC9S12E256MFUE Freescale Semiconductor, MC9S12E256MFUE Datasheet - Page 101

• Manufacturer Part Number: MC9S12E256MFUE
• Description: IC MCU 256K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E256MFUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-QFP
• Processor Series: S12E
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 12
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• On-chip Dac: 2-ch x 8-bit
• Controller Family/series: HCS12/S12X
• No. Of I/o's: 60
• Ram Memory Size: 16KB
• Cpu Speed: 25MHz
• No. Of Timers: 3
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

2.3.2.14
This register is reserved for factory testing and is not accessible.
All bits read 0 and are not writable.
2.3.2.15
This register is reserved for factory testing and is not accessible.
All bits read 0 and are not writable.
2.4
2.4.1
Write and read operations are both used for the program, erase, erase verify, and data compress algorithms
described in this subsection. The program and erase algorithms are time controlled by a state machine
whose timebase, FCLK, is derived from the oscillator clock via a programmable divider. The command
register as well as the associated address and data registers operate as a buffer and a register (2-stage FIFO)
so that a second command along with the necessary data and address can be stored to the buffer while the
first command remains in progress. This pipelined operation allows a time optimization when
programming more than one word on a specific row in the Flash block as the high voltage generation can
be kept active in between two programming commands. The pipelined operation also allows a
simplification of command launching. Buffer empty as well as command completion are signalled by flags
in the Flash status register with interrupts generated, if enabled.
The next paragraphs describe:
Freescale Semiconductor
Reset
Reset
1. How to write the FCLKDIV register.
2. Command write sequences used to program, erase, and verify the Flash memory.
3. Valid Flash commands.
4. Effects resulting from illegal Flash command write sequences or aborting Flash operations.
W
W
R
R
Functional Description
Flash Command Operations
RESERVED3
RESERVED4
7
0
0
7
0
0
= Unimplemented or Reserved
= Unimplemented or Reserved
6
0
0
6
0
0
MC9S12E256 Data Sheet, Rev. 1.08
5
0
0
5
0
0
Figure 2-20. RESERVED3
Figure 2-21. RESERVED4
4
0
0
4
0
0
3
0
0
3
0
0
Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
2
0
0
2
0
0
1
0
0
1
0
0
0
0
0
0
0
0
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