MC9S12E256MFUE Freescale Semiconductor, MC9S12E256MFUE Datasheet - Page 443

• Manufacturer Part Number: MC9S12E256MFUE
• Description: IC MCU 256K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E256MFUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-QFP
• Processor Series: S12E
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 12
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• On-chip Dac: 2-ch x 8-bit
• Controller Family/series: HCS12/S12X
• No. Of I/o's: 60
• Ram Memory Size: 16KB
• Cpu Speed: 25MHz
• No. Of Timers: 3
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

14.5
This subsection describes how VREG controls the reset of the MCU.The reset values of registers and
signals are provided in
listed in
14.5.1
During chip power-up the digital core may not work if its supply voltage V
deassertion level (V
kept high until V
continues the start-up sequence. The power-on reset is active in all operation modes of VREG.
14.5.2
For details on low-voltage reset see
14.6
This subsection describes all interrupts originated by VREG.
The interrupt vectors requested by VREG are listed in
are defined at MCU level.
14.6.1
In FPM VREG monitors the input voltage V
LVDS is set to 1. Vice versa, LVDS is reset to 0 when V
indicated by flag LVIF = 1, is triggered by any change of the status bit LVDS if interrupt enable bit
LVIE = 1.
Freescale Semiconductor
Table
Resets
Interrupts
Power-On Reset
Low-Voltage Reset
LVI — Low-Voltage Interrupt
Low Voltage Interrupt (LVI)
14-4.
On entering the reduced-power mode, the LVIF is not cleared by the VREG.
Power-on reset
Low-voltage reset
DD
PORD
Interrupt Source
exceeds V
Reset Source
Section 14.3, “Memory Map and Register
). Therefore, signal POR which forces the other blocks of the device into reset is
PORD
Table 14-5. VREG — Interrupt Vectors
Table 14-4. VREG — Reset Sources
Section 14.4.6, “LVR — Low-Voltage
. Then POR becomes low and the reset generator of the device
MC9S12E256 Data Sheet, Rev. 1.08
Always active
Available only in full-performance mode
LVIE = 1; Available only in full-performance mode
DDA
. Whenever V
NOTE
Table
DDA
Local Enable
14-5. Vector addresses and interrupt priorities
Chapter 14 Dual Output Voltage Regulator (VREG3V3V2)
Local Enable
rises above level V
DDA
Definition”. Possible reset sources are
drops below level V
DD
Reset”.
is below the POR
LVID
. An interrupt,
LVIA
the status bit
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