MC9S12E256MFUE Freescale Semiconductor, MC9S12E256MFUE Datasheet - Page 332

• Manufacturer Part Number: MC9S12E256MFUE
• Description: IC MCU 256K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E256MFUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-QFP
• Processor Series: S12E
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 12
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• On-chip Dac: 2-ch x 8-bit
• Controller Family/series: HCS12/S12X
• No. Of I/o's: 60
• Ram Memory Size: 16KB
• Cpu Speed: 25MHz
• No. Of Timers: 3
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2)
11.3.2.7
Read and write anytime.
11.3.2.8
Read anytime. This register cannot be modified after the WP bit is set.
332
Module Base + 0x0006
Module Base + 0x0007
FFLAG[3:0]
QSMP[3:0]
6, 4, 2, 0
Reset
Reset
Field
Field
7–0
W
W
R
R
Fault x Pin Flag — This flag is set after the required number of samples have been detected after a rising edge
on the FAULTx pin. Writing a logic one to FFLAGx clears it. Writing a logic zero has no effect. The fault protection
is enabled when FPINEx is set even when the PWMs are not enabled; therefore, a fault will be latched in,
requiring to be cleared in order to prevent an interrupt.
0 No fault on the FAULTx pin.
1 Fault on the FAULTx pin.
Note: Clearing FFLAGx satisfies pending FFLAGx CPU interrupt requests.
where x is 0, 1, 2 and 3.
Fault x Qualifying Samples — This field indicates the number of consecutive samples taken at the FAULTx pin
to determine if a fault is detected. The first sample is qualified after two bus cycles from the time the fault is
present and each sample after that is taken every four bus cycles. See
where x is 0, 1, 2 and 3.
PMF Fault Status Register (PMFFSTA)
PMF Fault Qualifying Samples Register (PMFQSMP)
0
0
0
7
7
QSMP3
Figure 11-11. PMF Fault Qualifying Samples Register (PMFQSMP)
= Unimplemented or Reserved
FFLAG3
0
0
6
6
Figure 11-10. PMF Fault Flag Register (PMFFSTA)
Table 11-9. PMFQSMP Field Descriptions
Table 11-8. PMFFSTA Field Descriptions
MC9S12E256 Data Sheet, Rev. 1.08
0
0
0
5
5
QSMP2
FFLAG2
0
0
4
4
Description
Description
3
0
0
3
0
QSMP1
FFLAG1
Table
0
0
2
2
11-10.
Freescale Semiconductor
0
0
0
1
1
QSMP0
FFLAG0
0
0
0
0