SAF-C161S-L25M AA Infineon Technologies, SAF-C161S-L25M AA Datasheet - Page 28
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SAF-C161S-L25M AA
Manufacturer Part Number
SAF-C161S-L25M AA
Description
IC MCU 16BIT ROM/LESS MQFP-80-7
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet
1.SAF-C161S-L25M_AA.pdf
(75 pages)
Specifications of SAF-C161S-L25M AA
Core Processor
C166
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
63
Program Memory Type
ROMless
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-SQFP
Data Bus Width
16 bit
Data Ram Size
2 KB
Interface Type
ASC, SSC
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
63
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Packages
PG-MQFP-80
Max Clock Frequency
25.0 MHz
Sram (incl. Cache)
2.0 KByte
Program Memory
0.0 KByte
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
F161SL25MAAXT
SAF-C161S-L25MAA
SAF-C161S-L25MAAINTR
SAF-C161S-L25MAATR
SAF-C161S-L25MAATR
SAFC161SL25MAAXT
SP000014947
SAF-C161S-L25MAA
SAF-C161S-L25MAAINTR
SAF-C161S-L25MAATR
SAF-C161S-L25MAATR
SAFC161SL25MAAXT
SP000014947
3.9
The Oscillator Watchdog (OWD) monitors the clock signal generated by the on-chip
oscillator (either with a crystal or via external clock drive). For this operation the PLL
provides a clock signal which is used to supervise transitions on the oscillator clock. This
PLL clock is independent from the XTAL1 clock. When the expected oscillator clock
transitions are missing the OWD activates the PLL Unlock / OWD interrupt node and
supplies the CPU with the PLL clock signal. Under these circumstances the PLL will
oscillate with its basic frequency.
In direct drive mode the PLL base frequency is used directly (
In prescaler mode the PLL base frequency is divided by 2 (
Note: The CPU clock source is only switched back to the oscillator clock after a
The oscillator watchdog can be disabled by setting bit OWDDIS in register SYSCON.
In this case (OWDDIS = ‘1’) the PLL remains idle and provides no clock signal, while the
CPU clock signal is derived directly from the oscillator clock or via prescaler or SDD. Also
no interrupt request will be generated in case of a missing oscillator clock.
Note: At the end of a reset bit OWDDIS reflects the inverted level of pin RD at that time.
Data Sheet
hardware reset.
Thus the oscillator watchdog may also be disabled via hardware by (externally)
pulling the RD line low upon a reset, similar to the standard reset configuration via
PORT0.
Oscillator Watchdog
24
f
CPU
f
CPU
Functional Description
= 1 … 2.5 MHz).
= 2 … 5 MHz).
V1.0, 2003-11
C161S