SAF-C161S-LM 3V AA Infineon Technologies, SAF-C161S-LM 3V AA Datasheet - Page 51

• Manufacturer Part Number: SAF-C161S-LM 3V AA
• Description: IC MCU 16BIT ROM/LESS MQFP-80-7
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161S-LM 3V AA

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-SQFP
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: ASC, SSC
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 63
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Packages: PG-MQFP-80
• Max Clock Frequency: 20.0 MHz
• Sram (incl. Cache): 2.0 KByte
• Program Memory: 0.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: F161SLM3VAAXT; SAF-C161S-LM3VAA; SAF-C161S-LM3VAAINTR; SAF-C161S-LM3VAATR; SAF-C161S-LM3VAATR; SAFC161SLM3VAAXT; SP000014948

Direct Drive
When direct drive is configured (CLKCFG = 011
disabled and the CPU clock is directly driven from the internal oscillator with the input
clock signal.
The frequency of
f
f
The timings listed below that refer to TCLs therefore must be calculated using the
minimum TCL that is possible under the respective circumstances. This minimum value
can be calculated via the following formula:
TCL
For two consecutive TCLs the deviation caused by the duty cycle of
so the duration of 2TCL is always 1/
used only once for timings that require an odd number of TCLs (1, 3, …). Timings that
require an even number of TCLs (2, 4, …) may use the formula 2TCL = 1/
Data Sheet
CPU
OSC
.
min
(i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock
= 1/
f
OSC
f
DC
CPU
min
directly follows the frequency of
(DC = duty cycle)
f
OSC
. The minimum value TCL
47
B
) the on-chip phase locked loop is
f
OSC
so the high and low time of
Timing Characteristics
min
f
OSC
therefore has to be
is compensated
f
V1.0, 2003-11
OSC
.
C161S
(2)