SAF-C161PI-L25M CA Infineon Technologies, SAF-C161PI-L25M CA Datasheet - Page 47
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SAF-C161PI-L25M CA
Manufacturer Part Number
SAF-C161PI-L25M CA
Description
IC MCU 16BIT ROM/LESS MQFP-100-2
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet
1.SAF-C161PI-LM_CA.pdf
(82 pages)
Specifications of SAF-C161PI-L25M CA
Core Processor
C166
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
76
Program Memory Type
ROMless
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-SQFP
Data Bus Width
16 bit
Data Ram Size
3 KB
Interface Type
ASC, I2C, SSC
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
76
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Packages
PG-MQFP-100
Max Clock Frequency
25.0 MHz
Sram (incl. Cache)
3.0 KByte
A / D Input Lines (incl. Fadc)
4
Program Memory
0.0 KByte
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
F161PIL25MCAXT
SAF-C161PI-L25MCA
SAF-C161PI-L25MCAINTR
SAF-C161PI-L25MCATR
SAF-C161PI-L25MCATR
SAFC161PIL25MCAXT
SP000014368
SAF-C161PI-L25MCA
SAF-C161PI-L25MCAINTR
SAF-C161PI-L25MCATR
SAF-C161PI-L25MCATR
SAFC161PIL25MCAXT
SP000014368
AC Characteristics
Definition of Internal Timing
The internal operation of the C161PI is controlled by the internal CPU clock f
edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles)
operations.
The specification of the external timing (AC Characteristics) therefore depends on the
time between two consecutive edges of the CPU clock, called “TCL” (see figure below).
Figure 11
The CPU clock signal
different mechanisms. The duration of TCLs and their variation (and also the derived
external timing) depends on the used mechanism to generate
be regarded when calculating the timings for the C161PI.
Note: The example for PLL operation shown in the fig. above refers to a PLL factor of 4.
The used mechanism to generate the CPU clock is selected during reset via the logic
levels on pins P0.15-13 (P0H.7-5).
The table below associates the combinations of these three bits with the respective clock
generation mode.
Data Sheet
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Generation Mechanisms for the CPU Clock
CPU
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TCL
CPU
. This influence must
TCL
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TCL TCL
CPU
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