SAF-C161PI-L25M CA Infineon Technologies, SAF-C161PI-L25M CA Datasheet - Page 49
![IC MCU 16BIT ROM/LESS MQFP-100-2](/photos/12/23/122321/saf-c161pi-l25m_ca_sml.jpg)
SAF-C161PI-L25M CA
Manufacturer Part Number
SAF-C161PI-L25M CA
Description
IC MCU 16BIT ROM/LESS MQFP-100-2
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet
1.SAF-C161PI-LM_CA.pdf
(82 pages)
Specifications of SAF-C161PI-L25M CA
Core Processor
C166
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
76
Program Memory Type
ROMless
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-SQFP
Data Bus Width
16 bit
Data Ram Size
3 KB
Interface Type
ASC, I2C, SSC
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
76
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Packages
PG-MQFP-100
Max Clock Frequency
25.0 MHz
Sram (incl. Cache)
3.0 KByte
A / D Input Lines (incl. Fadc)
4
Program Memory
0.0 KByte
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
F161PIL25MCAXT
SAF-C161PI-L25MCA
SAF-C161PI-L25MCAINTR
SAF-C161PI-L25MCATR
SAF-C161PI-L25MCATR
SAFC161PIL25MCAXT
SP000014368
SAF-C161PI-L25MCA
SAF-C161PI-L25MCAINTR
SAF-C161PI-L25MCATR
SAF-C161PI-L25MCATR
SAFC161PIL25MCAXT
SP000014368
The timings listed in the AC Characteristics that refer to TCLs therefore must be
calculated using the minimum TCL that is possible under the respective circumstances.
The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency so it corresponds to the applied input frequency
(crystal or oscillator) the relative deviation for periods of more than one TCL is lower than
for one single TCL (see formula and figure below).
For a period of N * TCL the minimum value is computed using the corresponding
deviation D
where N = number of consecutive TCLs
So for a period of 3 TCLs @ 25 MHz (i.e. N = 3): D
and (3TCL)
This is especially important for bus cycles using waitstates and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is neglectible.
Note: For all periods longer than 40 TCL the N=40 value can be used (see figure below).
Figure 12
Data Sheet
26.5
20
10
1
( N * TCL)
1
Max.jitter D [ns]
This approximated formula is valid for
1
N
min
:
5
Approximated Maximum Accumulated PLL Jitter
= 3TCL
min
40 and 10MHz
= N * TCL
10
NOM
- 1.288 ns = 58.7 ns (@
NOM
f
CPU
- D
20
N
25MHz.
47
and 1
D
N
[ns] = (13.3 + N *6.3) /
3
N
CPU
= (13.3 + 3 * 6.3) / 25 = 1.288 ns,
40.
= 25 MHz).
40
CPU
[MHz],
10 MHz
16 MHz
20 MHz
25 MHz
&3,
1999-07
N