SAF-C161PI-L25M CA Infineon Technologies, SAF-C161PI-L25M CA Datasheet - Page 78
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SAF-C161PI-L25M CA
Manufacturer Part Number
SAF-C161PI-L25M CA
Description
IC MCU 16BIT ROM/LESS MQFP-100-2
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet
1.SAF-C161PI-LM_CA.pdf
(82 pages)
Specifications of SAF-C161PI-L25M CA
Core Processor
C166
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
76
Program Memory Type
ROMless
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-SQFP
Data Bus Width
16 bit
Data Ram Size
3 KB
Interface Type
ASC, I2C, SSC
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
76
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Packages
PG-MQFP-100
Max Clock Frequency
25.0 MHz
Sram (incl. Cache)
3.0 KByte
A / D Input Lines (incl. Fadc)
4
Program Memory
0.0 KByte
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
F161PIL25MCAXT
SAF-C161PI-L25MCA
SAF-C161PI-L25MCAINTR
SAF-C161PI-L25MCATR
SAF-C161PI-L25MCATR
SAFC161PIL25MCAXT
SP000014368
SAF-C161PI-L25MCA
SAF-C161PI-L25MCAINTR
SAF-C161PI-L25MCATR
SAF-C161PI-L25MCATR
SAFC161PIL25MCAXT
SP000014368
Data Sheet
Figure 24
Notes
1)
2)
3)
4)
5)
6)
7)
Command
CLKOUT
Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).
The leading edge of the respective command depends on RW-delay.
READY sampled HIGH at this sampling point generates a READY controlled waitstate,
READY sampled LOW at this sampling point terminates the currently running bus cycle.
READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or
WR).
If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT
(e.g. because CLKOUT is not enabled), it must fulfill
if READY is removed in reponse to the command (see Note
Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may
be inserted here.
For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without
MTTC waitstate this delay is zero.
The next external bus cycle may start here.
RD, WR
READY
READY
Async
Sync
ALE
CLKOUT and READY
58
32
3)
Running cycle
59
30
34
2)
33
31
35
58
5)
3)
3)
37
1)
36
59
76
37
29
in order to be safely synchronized. This is guaranteed,
35
4)
waitstate
READY
).
3)
36
MUX/Tristate
60
4)
see 6)
6)
&3,
7)
1999-07