EP9302-IQZ Cirrus Logic Inc, EP9302-IQZ Datasheet - Page 375

• Manufacturer Part Number: EP9302-IQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-IQZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: LQFP
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1253

RXDCurAdd
DS785UM1
31
15
Definition:
Bit Descriptions:
Address:
Chip Reset:
Soft Reset:
Definition:
Bit Descriptions:
30
14
29
13
28
12
Receive Descriptor Queue Current Length register. The Receive Descriptor
Queue Current Length defines the number of bytes between the Receive
Descriptor Current Address and the end of the receive descriptor queue. This
value is used internally to wrap the pointer back to the start of the queue. The
register should not normally be written.
RSVD:
RDCL:
0x8001_0098 - Read/Write
0x0000_0000
Unchanged
Receive Descriptor Current Address register. The Receive Current Descriptor
Address contains the pointer to the next entry to be read from the receive
descriptor queue. This should be set at initialization time to the required
starting point in the descriptor queue. During operation the MAC will update
this address following successful descriptor reads. Intermediate values in this
register will not necessarily align to descriptor boundaries, nor directly effect
the current descriptor in use because several descriptors may be buffered
inside the MAC.
RDCA:
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Reserved. Unknown During Read.
Receive Descriptor Current Length.
Receive Descriptor Current Address.
24
8
RDCA
RDCA
23
7
22
6
21
1/10/100 Mbps Ethernet LAN Controller
5
20
4
19
3
EP93xx User’s Guide
18
2
17
1
16
9-73
0
9