EP9302-IQZ Cirrus Logic Inc, EP9302-IQZ Datasheet - Page 460

• Manufacturer Part Number: EP9302-IQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-IQZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: LQFP
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1253

11
HcHCCA
HcPeriodCurrentED
11-20
Universal Serial Bus Host Controller
EP93xx User’s Guide
31
15
31
15
Address:
Default:
Definition:
Bit Description:
Address:
30
14
30
14
29
13
29
13
28
12
28
12
FNO:
RHSC:
OC:
MIE:
0x8002_0018
0x0000_0000
Base physical address of the Host Controller Communication Area.
RSVD:
AD:
0x8002_001C
AD
27
27
11
11
26
10
26
10
AD
Copyright 2007 Cirrus Logic
25
25
9
9
FrameNumberOverflow: Disable interrupt generation due
to Frame Number Overflow.
RootHubStatusChange: Disable interrupt generation due
to Ownership Change.
OwnershipChange. Enable interrupt generation due to
Ownership Change.
Master Interrupt Enable: A zero written to this field is
ignored by HC. A one written to this field disables interrupt
generation due to events specified in the other bits of this
register. This field is set after a hardware or software reset.
Reserved. Unknown During Read.
HCCA. Base physical address of the Host Controller
Communication Area.
24
24
8
8
AD
AD
23
23
7
7
22
22
6
6
21
21
5
5
20
20
4
4
RSVD
19
19
3
3
18
18
2
2
RSVD
17
17
1
1
DS785UM1
16
16
0
0