EP9302-IQZ Cirrus Logic Inc, EP9302-IQZ Datasheet - Page 591

• Manufacturer Part Number: EP9302-IQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-IQZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: LQFP
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1253

DS785UM1
CRCApd:
IDLE:
AME:
RXE:
TXE:
TUS:
CRCE:
CRCS:
Copyright 2007 Cirrus Logic
CRC pass through.
0 - Do not pass received CRC to CPU.
1 - Pass received CRC to CPU.
Idle mode.
0 - Idle-in Mark mode - When HDLC is idle (not
transmitting start or stop flags or packets), hold the
transmit data pin high.
1 - Idle-in Flag mode - When HDLC is idle, transmit
continuous flags.
Address Match Enable. Activates address matching on
received frames.
00 - No address matching
01 - 4 x 1 byte matching
10 - 2 x 2 byte matching
11 - Undefined, no matching
HDLC Receive Enable.
0 - Disable HDLC RX. If UART is still enabled, UART may
still receive normally.
1 - Enable HDLC RX.
HDLC Transmit Enable.
0 - Disable HDLC TX. If UART is still enabled, UART may
still transmit normally.
1 - Enable HDLC TX.
Transmit FIFO Underrun Select
0 - TX FIFO underrun causes CRC (if enabled) and stop
flag to be transmitted.
1 - TX FIFO underrun causes abort (escape-flag) to be
transmitted.
CRC enable.
0 - No CRC generated by HDLC TX or expected by HDLC
RX.
1 - HDLC TX automatically generates and sends a CRC at
the end of a packet, and HDLC RX expects a CRC at the
end of a packet.
CRC size.
0 - CRC-16: x
1 - CRC-32: x
x
8
+ x
7
+ x
5
+ x
16
32
4
+ x
+ x
+ x
12
26
2
+ x + 1
+ x
+ x
5
23
+ 1
+ x
22
+ x
UART3 With HDLC Encoder
16
+ x
EP93xx User’s Guide
12
+ x
11
+ x
10
16-15
+
16