EP9302-IQZ Cirrus Logic Inc, EP9302-IQZ Datasheet - Page 804

• Manufacturer Part Number: EP9302-IQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-IQZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: LQFP
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1253

28
GPIOxEOI
GPIOxDB
28-14
GPIO Interface
EP93xx User’s Guide
31
15
31
15
Address:
Definition:
Bit Descriptions:
Address:
Definition:
In order to clear an edge sensitive interrupt that can occur over port A/B/F, the user must
write a data value of “1” to the corresponding bit in the GPIOxEOI register bit. The user must
clear an interrupt before changing Port A/B/F from interrupt mode to GPIO mode as the
interrupts are cleared once this change has occurred. Once an interrupt has occurred and the
interrupt service routine has started, one of the first instructions should be a write to this
location in order to clear the interrupt so that subsequent interrupts on the same line are not
missed.
For each port, if interrupts are enabled, it is possible to debounce the input signal. Setting a
bit in this register enables debouncing for the corresponding interrupt signal; clearing the bit
disables debouncing. Debouncing is implemented by passing the input signal through a 2-bit
shift register clocked by a 128 Hz clock.
30
14
30
14
29
13
29
13
28
12
28
12
RSVD
RSVD
GPIOAEOI: 0x8084_0098 - Write Only
GPIOBEOI: 0x8084_00B4 - Write Only
GPIOFEOI: 0x8084_0054 - Write Only
RSVD:
PxINTC:
GPIOADB: 0x8084_00A8 - Read/Write
GPIOBDB: 0x8084_00C4 - Read/Write
GPIOFDB: 0x8084_0064 - Read/Write
27
27
11
11
26
10
26
10
25
25
9
9
Copyright 2007 Cirrus Logic
Reserved. Unknown During Read.
Clears Interrupts
24
24
8
8
RSVD
RSVD
23
23
7
7
22
22
6
6
21
21
5
5
20
20
4
4
PxINTDB
PxINTC
19
19
3
3
18
18
2
2
17
17
1
1
DS785UM1
16
16
0
0