EP9302-IQZ Cirrus Logic Inc, EP9302-IQZ Datasheet - Page 447

• Manufacturer Part Number: EP9302-IQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-IQZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: LQFP
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1253

DS785UM1
11.2.3.3 List Management
11.2.3.4 Root Hub
A portion of the bandwidth is reserved for nonperiodic transfers. This ensures that some
amount of bulk and control transfers will occur in each frame period. The frame period is
defined for USB to be 1.0 ms.
The bandwidth allocation policy for OpenHCI is shown in
the Host Controller sending the Start of Frame (SOF) synchronization packet to the USB bus.
This is followed by the Host Controller servicing nonperiodic transfers until the frame interval
counter reaches the value set by the Host Controller Driver, indicating that the Host Controller
should begin servicing periodic transfers. After the periodic transfers complete, any
remaining time in the frame is consumed by servicing nonperiodic transfers once more.
The transport mechanism for USB data packets is via Transfer Descriptor queues linked to
Endpoint Descriptor lists. The Host Controller Driver creates these data structures then
passes control to the Host Controller for processing.
The Host Controller Driver is responsible for enqueuing and dequeuing Endpoint Descriptors.
Enqueuing is done by adding the Endpoint Descriptor to the tail of the appropriate list. This
may occur simultaneously with the Host Controller processing the list without requiring any
lock mechanism. Before dequeuing an Endpoint Descriptor, the Host Controller Driver may
disable the Host Controller from processing the entire Endpoint Descriptor list of the data type
being removed to ensure that the Host Controller is not accessing the Endpoint Descriptor.
The Host Controller Driver is also responsible for enqueuing Transfer Descriptors to the
appropriate Endpoint Descriptor. Enqueuing is done by adding the Transfer Descriptor to the
tail of the appropriate queue. This may occur simultaneously to the Host Controller
processing the queue without requiring any lock mechanism. Under normal operation, the
Host Controller dequeues the Transfer Descriptor. However, the Host Controller Driver
dequeues the Transfer Descriptor when the Transfer Descriptor is being canceled due to a
request from the client software or certain error conditions. In this instance, the Endpoint
Descriptor is disabled prior to the Transfer Descriptor being dequeued.
The Root Hub is integrated into the HC. The internal registers of the Root Hub are exposed to
the Host Controller Driver which is responsible for providing the proper hub-class protocol
with the USB Driver and proper control of the Root Hub.
SOF
Time
NP
Table 11-1. Frame Bandwidth Allocation
Copyright 2007 Cirrus Logic
Periodic
1 msec.
Table
Universal Serial Bus Host Controller
11-1. Each frame begins with
NP
EP93xx User’s Guide
11-7
11