EP9302-IQZ Cirrus Logic Inc, EP9302-IQZ Datasheet - Page 416

• Manufacturer Part Number: EP9302-IQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-IQZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: LQFP
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1253

10
Register Descriptions
CONTROL
10-22
DMA Controller
EP93xx User’s Guide
31
15
Address:
Definition:
Bit Descriptions:
30
14
29
13
28
12
Channel Base Address + 0x0000 - Read/Write
This is the Channel Control Register, used to configure the DMA Channel.
Important Programming Note: The control register should be read
immediately after being written. This action will allow hardware state machines
to transition and prevent a potential problem when the registers are being
written in back to back clock cycles.
RSVD:
STALLIntEn:
NFBIntEn:
ChErrorIntEn:
ENABLE:
RSVD
27
11
26
10
25
9
Copyright 2007 Cirrus Logic
24
Reserved. Unknown During Read.
Setting this bit to 1 enables the generation of the STALL
interrupt in the STALL State of the DMA Channel State
machine. Setting this bit to zero disables generation of the
STALL Interrupt.
Setting this bit to 1 enables the generation of the NFB
(next frame buffer) interrupt in the ON State of the DMA
Channel State machine. Setting this bit to zero disables
generation of the NFB Interrupt. Normally when the
channel is enabled, this bit should be 1. However in the
case where the current buffer is the last, then this bit can
be cleared to prevent the generation of an interrupt while
the DMA State machine is in the ON State.
Setting this bit to 1 enables the ChError Interrupt which
indicates if the buffer transfer occurred with an error.
Setting this bit to 1 enables the channel, clearing this bit
disables channel, and causes the remaining
unpacker/packer data to be discarded. The channel must
always be enabled before writing the Base address
register.
8
23
7
RSVD
ICE
22
6
ABORT
21
5
ENABLE
20
4
ChErrorIntEn
19
3
RSVD
18
2
NFBIntEn
17
1
DS785UM1
STALLIntEn
16
0