ST10R167-Q3 STMicroelectronics, ST10R167-Q3 Datasheet - Page 19

• Manufacturer Part Number: ST10R167-Q3
• Description: IC MCU 16BIT ROMLESS 144-PQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10R167-Q3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-QFP
• Processor Series: ST10R1x
• Core: ST10
• Data Bus Width: 16 bit
• Program Memory Size: 32 KB
• Data Ram Size: 4 KB
• Interface Type: CAN/SSC/USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-2043

IX - GENERAL PURPOSE TIMER UNIT (continued)
Figure 5 : Block diagram of GPT1
IX.2 - GPT2
The GPT2 module provides precise event control
and time measurement. It includes two timers (T5,
T6) and a capture/reload register (CAPREL). Both
timers can be clocked with an input clock which is
derived from the CPU clock via a programmable
prescaler or with external signals. The count
direction (up/down) for each timer is programma-
ble by software or may additionally be altered
dynamically by an external signal on a port pin
(TxEUD). Concatenation of the timers is sup-
ported via the output toggle latch (T6OTL) of timer
T6 which changes its state on each timer over-
flow/underflow.
The state of this latch may be used to clock timer
T5, or it may be output on a port pin (T6OUT). The
overflows/underflows of timer T6 can additionally
be used to clock the CAPCOM timers T0 or T1,
and to cause a reload from the CAPREL register.
CPU Clock
CPU Clock
CPU Clock
T2EUD
T3IN
T3EUD
T4EUD
T2IN
T4IN
2
2
2
n
n
n
n=3...10
n=3...10
n=3...10
T3
Mode
Control
T4
Mode
Control
T2
Mode
Control
Reload
Capture
Reload
Capture
The CAPREL register may capture the contents of
timer T5 based on an external signal transition on
the corresponding port pin (CAPIN), and timer T5
may optionally be cleared after the capture proce-
dure. This allows absolute time differences to be
measured or pulse multiplication to be performed
without software overhead.
The capture trigger (timer T5 to CAPREL) may
also be generated upon transitions of GPT1 timer
T3 inputs T3IN and/or T3EUD. This is advanta-
geous when T3 operates in Incremental Interface
Mode.
Table 7 lists the timer input frequencies, resolution
and periods for each pre-scaler option at 25MHz
CPU clock.
This also applies to the Gated Timer Mode of T6
and to the auxiliary timer T5 in Timer and Gated
Timer Mode.
U/D
GPT1 Timer T3
GPT1 Timer T4
GPT1 Timer T2
U/D
U/D
T3OTL
Interrupt
Request
Interrupt
Request
Request
Interrupt
T3OUT
ST10R167
19/63