ST10R167-Q3 STMicroelectronics, ST10R167-Q3 Datasheet - Page 53
ST10R167-Q3
Manufacturer Part Number
ST10R167-Q3
Description
IC MCU 16BIT ROMLESS 144-PQFP
Manufacturer
STMicroelectronics
Series
ST10r
Datasheet
1.ST10R167-Q3.pdf
(63 pages)
Specifications of ST10R167-Q3
Core Processor
ST10
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
111
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
144-QFP
Processor Series
ST10R1x
Core
ST10
Data Bus Width
16 bit
Program Memory Size
32 KB
Data Ram Size
4 KB
Interface Type
CAN/SSC/USART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
111
Number Of Timers
5
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
497-2043
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST10R167-Q3
Manufacturer:
ST
Quantity:
556
Company:
Part Number:
ST10R167-Q3
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
ST10R167-Q3
Manufacturer:
ST
Quantity:
20 000
Company:
Part Number:
ST10R167-Q3/TR
Manufacturer:
STMicroelectronics
Quantity:
10 000
Company:
Part Number:
ST10R167-Q3B0
Manufacturer:
ST
Quantity:
1 343
Part Number:
ST10R167-Q3B0
Manufacturer:
ST
Quantity:
20 000
Table 19 : Demultiplexed bus characteristics (continued)
Notes 1. Guaranteed by design characterization.
t
t
t
t
t
t
t
t
t
t
t
53
68
Symbol
43
46
47
48
49
50
51
55
57
1
1
2. RW-delay and tA refer to the next following bus cycle.
3. Read data is latched with the same clock edge that triggers the address change and the rising RD edge. Therefore address
changes before the end of RD have no impact on read cycles.
CC
CC
CC
CC
CC
CC
SR
SR
SR
SR
SR
ALE falling edge to RdCS, WrCS
(no RW-delay)
RdCS to Valid Data In (with
RW-delay)
RdCS to Valid Data In (no
RW-delay)
RdCS, WrCS Low Time (with
RW-delay)
RdCS, WrCS Low Time (no
RW-delay)
Data valid to WrCS
Data hold after RdCS
Data float after RdCS (with
RW-delay)
Data float after RdCS (no RW-delay)
Address hold after RdCS, WrCS
Data hold after WrCS
Parameter
-10 + t
30 + t
50 + t
26 + t
-4 + t
6 + t
Min.
Max. CPU Clock
–
–
0
–
–
F
A
C
C
C
F
= 25MHz
16 + t
36 + t
20 + t
0 + t
Max.
–
–
–
–
–
–
–
F
C
C
F
2TCL - 10 + t
3TCL - 10 + t
2TCL - 14 + t
TCL - 14 + t
-10 + t
-4 + t
1/2TCL = 1 to 25MHz
Min.
Variable CPU Clock
–
–
0
–
–
A
F
F
C
C
C
2TCL - 24 + t
3TCL - 24 + t
2TCL - 20 + t
TCL - 20 + t
Max.
–
–
–
–
–
–
–
ST10R167
F
C
C
F
53/63
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns