C8051T635-GM Silicon Laboratories Inc, C8051T635-GM Datasheet - Page 125

• Manufacturer Part Number: C8051T635-GM
• Description: IC MCU 2KB 20PIN QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051T63xr

Specifications of C8051T635-GM

• Program Memory Type: OTP
• Program Memory Size: 2KB (2K x 8)
• Package / Case: 20-QFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 17
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051T6x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051T630DK
• Minimum Operating Temperature: - 40 C
• Package: 20QFN EP
• Device Core: 8051
• Family Name: C8051T63x
• Maximum Speed: 25 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1464 - KIT DEV FOR C8051T630 FAMILY
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1463-5

SFR Definition 20.14. P1SKIP: Port 1 Skip
SFR Address = 0xD5
SFR Definition 20.15. P2: Port 2
SFR Address = 0xA0; Bit-Addressable
Name
Reset
Name
Reset
Bit
6:0
Bit
7:1
Type
Type
7
0
Bit
Bit
Unused
P1SKIP[6:0]
Name
P2[0]
Unused
Name
R
R
7
0
7
0
Unused.
Port 2 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
Unused. Read = 0b; Write = Don’t Care.
Port 1 Crossbar Skip Enable Bits.
These bits select Port 1 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P1.n pin is not skipped by the Crossbar.
1: Corresponding P1.n pin is skipped by the Crossbar.
R
6
0
6
0
Description
R
5
0
5
0
Rev. 1.0
Don’t Care
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
R
4
0
4
0
P1SKIP[6:0]
Function
Write
R/W
R
3
0
3
0
C8051T630/1/2/3/4/5
R
2
0
2
0
000000b
0: P2.0 Port pin is logic
LOW.
1: P2.0 Port pin is logic
HIGH.
R
1
0
1
0
Read
P2[0]
R/W
0
0
0
1
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