C8051T635-GM Silicon Laboratories Inc, C8051T635-GM Datasheet - Page 93

• Manufacturer Part Number: C8051T635-GM
• Description: IC MCU 2KB 20PIN QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051T63xr

Specifications of C8051T635-GM

• Program Memory Type: OTP
• Program Memory Size: 2KB (2K x 8)
• Package / Case: 20-QFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 17
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051T6x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051T630DK
• Minimum Operating Temperature: - 40 C
• Package: 20QFN EP
• Device Core: 8051
• Family Name: C8051T63x
• Maximum Speed: 25 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1464 - KIT DEV FOR C8051T630 FAMILY
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1463-5

C8051T630/1/2/3/4/5
software prior to entering the idle mode if the WDT was initially configured to allow this operation. This pro-
vides the opportunity for additional power savings, allowing the system to remain in the idle mode indefi-
nitely, waiting for an external stimulus to wake up the system. Refer to Section “18.6. PCA Watchdog Timer
Reset” on page 99 for more information on the use and configuration of the WDT.
17.2. Stop Mode
Setting the Stop Mode Select bit (PCON.1) causes the controller core to enter stop mode as soon as the
instruction that sets the bit completes execution. In stop mode the internal oscillator, CPU, and all digital
peripherals are stopped; the state of the external oscillator circuit is not affected. Each analog peripheral
(including the external oscillator circuit) may be shut down individually prior to entering stop mode. Stop
mode can only be terminated by an internal or external reset. On reset, the device performs the normal
reset sequence and begins program execution at address 0x0000.
If enabled, the missing clock detector will cause an internal reset and thereby terminate the stop mode.
The missing clock detector should be disabled if the CPU is to be put to in stop mode for longer than the
MCD timeout.
By default, when in stop mode the internal regulator is still active. However, the regulator can be config-
ured to shut down while in stop mode to save power. To shut down the regulator in stop mode, the
STOPCF bit in register REG0CN should be set to 1 prior to setting the STOP bit (see SFR Definition 10.1).
If the regulator is shut down using the STOPCF bit, only the RST pin or a full power cycle are capable of
resetting the device.
17.3. Suspend Mode
Setting the SUSPEND bit (OSCICN.5) causes the hardware to halt the CPU and the high-frequency inter-
nal oscillator, and go into suspend mode as soon as the instruction that sets the bit completes execution.
All internal registers and memory maintain their original data. Most digital peripherals are not active in sus-
pend mode. The exception to this is the Port Match feature and Timer 3, when it is run from an external
oscillator source or the internal low-frequency oscillator.
Suspend mode can be terminated by four types of events, a port match (described in Section “20.5. Port
Match” on page 118), a Timer 3 overflow (described in Section “24.3. Timer 3” on page 185), a comparator
low output (if enabled), or a device reset event. To run Timer 3 in suspend mode, the timer must be config-
ured to clock from either the external clock source or the internal low-frequency oscillator source. When
suspend mode is terminated, the device will continue execution on the instruction following the one that set
the SUSPEND bit. If the wake event (port match or Timer 3 overflow) was configured to generate an inter-
rupt, the interrupt will be serviced upon waking the device. If suspend mode is terminated by an internal or
external reset, the CIP-51 performs a normal reset sequence and begins program execution at address
0x0000.
Rev. 1.0
93