C8051T635-GM Silicon Laboratories Inc, C8051T635-GM Datasheet - Page 98

• Manufacturer Part Number: C8051T635-GM
• Description: IC MCU 2KB 20PIN QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051T63xr

Specifications of C8051T635-GM

• Program Memory Type: OTP
• Program Memory Size: 2KB (2K x 8)
• Package / Case: 20-QFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 17
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051T6x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051T630DK
• Minimum Operating Temperature: - 40 C
• Package: 20QFN EP
• Device Core: 8051
• Family Name: C8051T63x
• Maximum Speed: 25 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1464 - KIT DEV FOR C8051T630 FAMILY
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1463-5

C8051T630/1/2/3/4/5
SFR Definition 18.1. VDM0CN: V
SFR Address = 0xFF
18.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-
ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Table 5.4 for complete RST pin spec-
ifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
18.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than 100 µs, the one-shot will time out and generate a reset. After a
MCD reset, the MCDRSF flag (RSTSRC.2) will read 1, signifying the MCD as the reset source; otherwise,
this bit reads 0. Writing a 1 to the MCDRSF bit enables the Missing Clock Detector; writing a 0 disables it.
The state of the RST pin is unaffected by this reset.
98
Name
Reset
5:0
Bit
Type
7
6
Bit
VDDSTAT
VDMEN
Unused
VDMEN
Name
Varies
R/W
7
VDDSTAT
V
This bit turns the V
tem resets until it is also selected as a reset source in register RSTSRC (SFR Def-
inition 18.2). Selecting the V
may generate a system reset. In systems where this reset would be undesirable, a
delay should be introduced between enabling the V
reset source. See Table 5.4 for the minimum V
0: V
1: V
V
This bit indicates the current power supply status (V
0: V
1: V
Unused. Read = 000000b; Write = Don’t care.
Varies
DD
DD
R
6
DD
DD
DD
DD
Monitor Enable.
Status.
Monitor Disabled.
Monitor Enabled.
is at or below the V
is above the V
R
5
0
DD
DD
DD
monitor circuit on/off. The V
Monitor Control
monitor threshold.
Rev. 1.0
DD
R
4
0
DD
monitor threshold.
monitor as a reset source before it has stabilized
Function
R
3
0
DD
DD
Monitor turn-on time.
R
2
0
DD
DD
Monitor cannot generate sys-
Monitor and selecting it as a
Monitor output).
R
1
0
R
0
0