C8051T635-GM Silicon Laboratories Inc, C8051T635-GM Datasheet - Page 73

• Manufacturer Part Number: C8051T635-GM
• Description: IC MCU 2KB 20PIN QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051T63xr

Specifications of C8051T635-GM

• Program Memory Type: OTP
• Program Memory Size: 2KB (2K x 8)
• Package / Case: 20-QFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 17
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051T6x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051T630DK
• Minimum Operating Temperature: - 40 C
• Package: 20QFN EP
• Device Core: 8051
• Family Name: C8051T63x
• Maximum Speed: 25 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1464 - KIT DEV FOR C8051T630 FAMILY
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1463-5

13.1. Program Memory
The CIP-51 core has a 64 kB program memory space. The C8051T630/1 implements 8192 bytes of this
program memory space as in-system, Byte-Programmable EPROM, organized in a contiguous block from
addresses 0x0000 to 0x1FFF. Note that 512 bytes (0x1E00 – 0x1FFF) of this memory are reserved for fac-
tory use and are not available for user program storage. The C8051T632/3 implements 4096 bytes of
EPROM program memory space; the C8051T634/5 implements 2048 bytes of EPROM program memory
space. C2 Register Definition 13.2 shows the program memory maps for C8051T630/1/2/3/4/5 devices.
Program memory is read-only from within firmware. Individual program memory bytes can be read using
the MOVC instruction. This facilitates the use of EPROM space for constant storage.
13.2. Data Memory
The C8051T630/1/2/3/4/5 device family includes 768 bytes of RAM data memory. 256 bytes of this mem-
ory is mapped into the internal RAM space of the 8051. 512 bytes of this memory is on-chip “external”
memory. The data memory map is shown in Figure 13.1 for reference.
13.2.1. Internal RAM
There are 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The
lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either
direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00
through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight
byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as bytes or
as 128 bit locations accessible with the direct addressing mode.
The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the
same address space as the Special Function Registers (SFR) but is physically separate from the SFR
space. The addressing mode used by an instruction when accessing locations above 0x7F determines
whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use
direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the
upper 128 bytes of data memory. Figure 13.1 illustrates the data memory organization of the
C8051T630/1/2/3/4/5.
EPROM Memory
C8051T630/1
Security Byte
7680 Bytes
Reserved
0x1FFF
0x1FFE
0x1E00
0x1DFF
0x0000
Figure 13.2. Program Memory Map
EPROM Memory
C8051T632/3
Security Byte
4096 Bytes
Reserved
Rev. 1.0
0x1FFF
0x1FFE
0x1000
0x0FFF
0x0000
C8051T630/1/2/3/4/5
EPROM Memory
C8051T634/5
Security Byte
2048 Bytes
Reserved
0x1FFF
0x1FFE
0x0800
0x07FF
0x0000
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