C8051F901-GU Silicon Laboratories Inc, C8051F901-GU Datasheet
C8051F901-GU
Specifications of C8051F901-GU
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C8051F901-GU Summary of contents
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Single/Dual Battery, 0.9–3.6 V, 16–8 kB, SmaRTClock, 12/10-Bit ADC MCU Ultra-Low Power - 160 uA/MHz in active mode (24.5 MHz clock wake-up time (two-cell mode sleep mode with memory retention sleep ...
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C8051F91x-C8051F90x 2 Rev. 1.0 ...
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Table of Contents 1. System Overview.................................................................................................... 17 1.1. CIP-51™ Microcontroller Core.......................................................................... 20 1.1.1. Fully 8051 Compatible.............................................................................. 20 1.1.2. Improved Throughput ............................................................................... 20 1.1.3. Additional Features .................................................................................. 20 1.2. Port Input/Output............................................................................................... 21 1.3. Serial Ports ....................................................................................................... 22 1.4. Programmable Counter Array ...
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C8051F91x-C8051F90x 6.2. IREF0 Specifications......................................................................................... 87 7. Comparators ........................................................................................................... 88 7.1. Comparator Inputs ............................................................................................ 88 7.2. Comparator Outputs ......................................................................................... 89 7.3. Comparator Response Time............................................................................. 90 7.4. Comparator Hysteresis ..................................................................................... 90 7.5. Comparator Register Descriptions.................................................................... 91 7.6. Comparator0 and Comparator1 Analog Multiplexers........................................ ...
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Clock ......................................................................................... 138 13.6.Minimizing Flash Read Current ...................................................................... 139 14. Power Management.............................................................................................. 143 14.1.Normal Mode .................................................................................................. 144 14.2.Idle Mode........................................................................................................ 145 14.3.Stop Mode ...................................................................................................... 145 14.4.Suspend Mode ............................................................................................... 146 14.5.Sleep Mode .................................................................................................... 146 14.6.Configuring Wakeup Sources......................................................................... 147 14.7.Determining the Event ...
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C8051F91x-C8051F90x 19.2.Low Power Internal Oscillator......................................................................... 180 19.3.External Oscillator Drive Circuit...................................................................... 180 19.3.1.External Crystal Mode............................................................................ 180 19.3.2.External RC Mode.................................................................................. 182 19.3.3.External Capacitor Mode........................................................................ 183 19.3.4.External CMOS Clock Mode .................................................................. 184 19.4.Special Function Registers for Selecting and Configuring the System Clock 185 ...
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Operation ........................................................................................... 227 22.3.1.Transmitter Vs. Receiver........................................................................ 227 22.3.2.Arbitration............................................................................................... 227 22.3.3.Clock Low Extension.............................................................................. 228 22.3.4.SCL Low Timeout................................................................................... 228 22.3.5.SCL High (SMBus Free) Timeout .......................................................... 228 22.4.Using the SMBus............................................................................................ 229 22.4.1.SMBus Configuration Register............................................................... 230 22.4.2.SMB0CN Control Register ..................................................................... 233 22.4.3.Hardware Slave ...
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C8051F91x-C8051F90x 25.3.1.16-bit Timer with Auto-Reload................................................................ 286 25.3.2.8-bit Timers with Auto-Reload................................................................ 287 25.3.3.Comparator 1/External Oscillator Capture Mode ................................... 288 26. Programmable Counter Array ............................................................................. 292 26.1.PCA Counter/Timer ........................................................................................ 293 26.2.PCA0 Interrupt Sources.................................................................................. 294 26.3.Capture/Compare Modules ............................................................................ 296 26.3.1.Edge-triggered Capture Mode................................................................ 297 ...
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... List of Figures Figure 1.1. C8051F912 Block Diagram .................................................................... 18 Figure 1.2. C8051F911 Block Diagram .................................................................... 18 Figure 1.3. C8051F902 Block Diagram .................................................................... 19 Figure 1.4. C8051F901 Block Diagram .................................................................... 19 Figure 1.5. Port I/O Functional Block Diagram ......................................................... 21 Figure 1.6. PCA Block Diagram................................................................................ 22 Figure 1.7. ADC0 Functional Block Diagram............................................................ 23 Figure 1.8. ADC0 Multiplexer Block Diagram ........................................................... 24 Figure 1 ...
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C8051F91x-C8051F90x Figure 13.1. Flash Program Memory Map (16 kB and 8 kB devices)..................... 134 Figure 14.1. C8051F91x-C8051F90x Power Distribution....................................... 144 Figure 15.1. CRC0 Block Diagram ......................................................................... 152 Figure 15.2. Bit Reverse Register .......................................................................... 159 Figure 16.1. DC-DC Converter Block Diagram....................................................... ...
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Figure 25.2. T0 Mode 2 Block Diagram.................................................................. 274 Figure 25.3. T0 Mode 3 Block Diagram.................................................................. 275 Figure 25.4. Timer 2 16-Bit Mode Block Diagram .................................................. 280 Figure 25.5. Timer 2 8-Bit Mode Block Diagram .................................................... 281 Figure 25.6. Timer 2 ...
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C8051F91x-C8051F90x List of Tables ...
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Table 22.2. Minimum SDA Setup and Hold Times . . . . . . . . . . . . . . . . . . . . . . . . 231 Table 22.3. Sources for Hardware Changes to ...
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C8051F91x-C8051F90x List of Registers SFR Definition 5.1. ADC0CN: ADC0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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SFR Definition 14.2. PMU0MD: Power Management Unit Mode . . . . . . . . . . . . . . . . 150 SFR Definition 14.3. PCON: Power Management Control Register . . . . . . . ...
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C8051F91x-C8051F90x SFR Definition 21.19. P2MDOUT: Port2 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 224 SFR Definition 21.20. P2DRV: Port2 Drive Strength ...
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System Overview C8051F91x-C8051F90x devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features are listed below. Refer to Table 2.1 for specific product feature selection and part ordering numbers. • Single/Dual Battery operation with on-chip dc-dc boost converter. • High-speed ...
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C8051F91x-C8051F90x CIP-51 8051 Power On Controller Core Reset/PMU 16k Byte ISP Flash Wake Program Memory Reset 256 Byte SRAM Debug / C2CK/RST Programming 512 Byte XRAM Hardware C2D Power Net VDD/DC+ VREG Analog Digital Power Power GND/DC- Precision 24.5 MHz ...
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... Converter VBAT 20 MHz Oscillator GND External XTAL1 Oscillator XTAL2 Circuit XTAL3 SmaRTClock Oscillator XTAL4 System Clock Configuration Figure 1.4. C8051F901 Block Diagram C8051F91x-C8051F90x Port I/O Configuration Digital Peripherals UART Timers Priority Crossbar PCA/ Decoder WDT CRC SMBus SPI 0,1 Crossbar Control ...
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C8051F91x-C8051F90x 1.1. CIP-51™ Microcontroller Core 1.1.1. Fully 8051 Compatible The C8051F91x-C8051F90x family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop ...
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Port Input/Output Digital and analog resources are available through 16 I/O pins. Port pins are organized as three byte-wide ports. Port pins P0.0–P1.6 can be defined as digital or analog I/O. Digital I/O pins can be assigned to one ...
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C8051F91x-C8051F90x 1.3. Serial Ports The C8051F91x-C8051F90x Family includes an SMBus/I baud rate configuration, and two Enhanced SPI interfaces. Each of the serial buses is fully implemented in hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little ...
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SAR ADC with 16-bit Auto-Averaging Accumulator and Autonomous Low Power Burst Mode C8051F91x-C8051F90x devices have a 300 ksps, 10-bit or 75 ksps 12-bit successive-approximation- register (SAR) ADC with integrated track-and-hold and programmable window detector. ADC0 also has an autonomous ...
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C8051F91x-C8051F90x P0.0 P1.6 Temp Sensor VBAT Digital Supply VDD/DC+ Figure 1.8. ADC0 Multiplexer Block Diagram 1.6. Programmable Current Reference (IREF0) C8051F91x-C8051F90x devices include an on-chip programmable current reference (source or sink) with two output current settings: low power mode and ...
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CP0EN CP0OUT CP0RIF CP0FIF CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 Analog Input Multiplexer Px.x CP0 + Px.x Px.x CP0 - Px.x Figure 1.9. Comparator 0 Functional Block Diagram CP1EN CP1OUT CP1RIF CP1FIF CP1HYP1 CP1HYP0 CP1HYN1 CP1HYN0 Analog Input Multiplexer Px.x CP1 + ...
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... C8051F902- 768 C8051F901- 768 C8051F901- 768 C8051F901- 768 *The 'F9xx Plus features are a set of enhancements that allow greater power efficiency and increased functionality. They include 12-bit ADC mode, PWM Enhanced IREF, ultra-low power SmaRTClock LFO, VBAT input voltage from 0.9 to 3.6 V, and VBAT battery low indicator. The 'F9xx Plus features are described in detail in " ...
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Pinout and Package Definitions Table 3.1. Pin Definitions for the C8051F91x-C8051F90x Pin Numbers ‘F912-GM ‘F912-GU Name ‘F902-GM ‘F902-GU ‘F911-GM ‘F911-GU ‘F901-GM ‘F901-GU VBAT DC+ DC– GND GND 2 5 ...
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C8051F91x-C8051F90x Table 3.1. Pin Definitions for the C8051F91x-C8051F90x (Continued) Pin Numbers ‘F912-GM ‘F912-GU Name ‘F902-GM ‘F902-GU ‘F911-GM ‘F911-GU ‘F901-GM ‘F901-GU XTAL3 9 12 XTAL4 REF P0 I/O or ...
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Table 3.1. Pin Definitions for the C8051F91x-C8051F90x (Continued) Pin Numbers ‘F912-GM ‘F912-GU Name ‘F902-GM ‘F902-GU ‘F911-GM ‘F911-GU ‘F901-GM ‘F901-GU P0 I/O or CNVSTR P0 I/O or IREF0 P1 I/O or P1.1 ...
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C8051F91x-C8051F90x GND/DC– 1 C8051F912/02-GM GND 2 C8051F911/01-GM VDD/DC+ 3 DCEN 4 GND (Optional Connection) VBAT 5 RST/C2CK 6 *Note: Signal only available on 'F912 and 'F902 devices. Figure 3.1. QFN-24 Pinout Diagram (Top View) 30 Top View Rev. 1.0 18 ...
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P0.2/XTAL1/RTCOUT* 1 P0.1/AGND 2 3 P0.0/VREF 4 GND/DC- GND 5 VDD/DC+ 6 DCEN 7 8 VBAT 9 RST/C2CK 10 P2.7/C2D 11 XTAL4 12 XTAL3 *Note: Signal only available on 'F912 and 'F902 devices. Figure 3.2. QSOP-24 Pinout Diagram F912 (Top ...
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C8051F91x-C8051F90x Figure 3.3. QFN-24 Package Drawing Table 3.2. QFN-24 Package Dimensions Dimension Min Typ A 0.70 0.75 A1 0.00 0.02 b 0.18 0.25 D 4.00 BSC D2 2.55 2.70 e 0.50 BSC E 4.00 BSC E2 2.55 2.70 Notes: 1. ...
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Figure 3.4. Typical QFN-24 Landing Diagram Table 3.3. PCB Land Pattern Dimension Min C1 3.90 C2 3.90 E 0.50 BSC Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is ...
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C8051F91x-C8051F90x Figure 3.5. QSOP-24 Package Diagram Table 3.4. QSOP-24 Package Dimensions Dimension Min Nom A — — A1 0.10 — b 0.20 — c 0.10 — D 8.65 BSC E 6.00 BSC E1 3.90 BSC Notes: 1. All dimensions shown ...
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Figure 3.6. QSOP-24 Landing Diagram Table 3.5. PCB Land Pattern Dimension Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This land pattern is based on the IPC-7351 guidelines. Solder Mask ...
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C8051F91x-C8051F90x 4. Electrical Characteristics Throughout the Electrical Characteristics chapter, “VDD” refers to the VDD/DC+ Supply Voltage. Blue indicates a feature only available on ‘F912 and ‘F902 devices. 4.1. Absolute Maximum Specifications Table 4.1. Absolute Maximum Ratings Parameter Ambient temperature under ...
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Electrical Characteristics Table 4.2. Global Electrical Characteristics –40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the ‘F9xx" for details on how to achieve the supply current specifications listed in ...
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C8051F91x-C8051F90x Table 4.2. Global Electrical Characteristics (Continued) –40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the ‘F9xx" for details on how to achieve the supply current specifications listed in this ...
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Table 4.2. Global Electrical Characteristics (Continued) –40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the ‘F9xx" for details on how to achieve the supply current specifications listed in this table. ...
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C8051F91x-C8051F90x Table 4.2. Global Electrical Characteristics (Continued) –40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the ‘F9xx" for details on how to achieve the supply current specifications listed in this ...
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F < 14 MHz 4000 Oneshot Enabled 3900 3800 3700 3600 3500 3400 3300 3200 3100 3000 2900 2800 2700 2600 2500 200 uA/MHz 2400 2300 2200 2100 2000 1900 1800 1700 1600 1500 1400 1300 215 uA/MHz ...
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C8051F91x-C8051F90x 4200 4100 4000 3900 3800 3700 3600 3500 3400 3300 3200 3100 3000 2900 2800 2700 2600 2500 2400 2300 2200 2100 2000 1900 1800 1700 1600 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 ...
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Figure 4.3. Typical DC-DC Converter Efficiency (High Current, VDD/DC C8051F91x-C8051F90x Load Current (mA) Rev. 1.0 43 ...
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C8051F91x-C8051F90x Figure 4.4. Typical DC-DC Converter Efficiency (High Current, VDD/DC Load current (mA) Rev. 1.0 ...
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Figure 4.5. Typical DC-DC Converter Efficiency (Low Current, VDD/DC C8051F91x-C8051F90x Load current (mA) Rev. 1.0 45 ...
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C8051F91x-C8051F90x Figure 4.6. Typical One-Cell Suspend Mode Current 46 Rev. 1.0 ...
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Table 4.3. Port I/O DC Electrical Characteristics V = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. DD Parameters Output High Voltage High Drive Strength, PnDRV IOH = –3 mA, Port I/O push-pull IOH = ...
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C8051F91x-C8051F90x 3.6 3.3 3 2.7 2.4 2.1 1.8 1.5 1.2 0 3.6 3.3 3 2.7 2.4 2.1 1.8 1.5 1.2 0 Figure 4.7. Typical VOH Curves, 1.8–3 Typical VOH (High Drive Mode) ...
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C8051F91x-C8051F90x Typical VOH (High Drive Mode) 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0 Load Current (mA) Typical VOH (Low Drive Mode) 1.8 1.7 1.6 1.5 ...
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C8051F91x-C8051F90x 1.8 1.5 1.2 0.9 0.6 0.3 0 -80 -70 1.8 1.5 1.2 0.9 0.6 0 Figure 4.9. Typical VOL Curves, 1.8–3 Typical VOL (High Drive Mode) VDD = 3.6V VDD = 3.0V VDD ...
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C8051F91x-C8051F90x Typical VOL (High Drive Mode) 0.5 VDD = 1.8V 0.4 VDD = 1.5V VDD = 1.2V 0.3 VDD = 0.9V 0.2 0 Load Current (mA) Typical VOL (Low Drive Mode) 0.5 0.4 0.3 VDD ...
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C8051F91x-C8051F90x Table 4.4. Reset Electrical Characteristics V = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. DD Parameter RST Output Low Voltage RST Input High Voltage RST Input Low Voltage RST Input Pullup Current VDD/DC+ Monitor Threshold ...
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Table 4.5. Power Management Electrical Specifications V = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. DD Parameter Idle Mode Wake-up Time Suspend Mode Wake-up Time Sleep Mode Wake-up Time Table 4.6. Flash Electrical Characteristics V = ...
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C8051F91x-C8051F90x Table 4.9. SmaRTClock Characteristics V = 1 –40 to +85 °C unless otherwise specified; Using factory-calibrated settings Parameter Oscillator Frequency (LFO) Blue Note: indicates a feature only available on ‘F912 and ‘F902 ...
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Table 4.10. ADC0 Electrical Characteristics (Continued 1.8 to 3.6V V, VREF = 1.65 V (REFSL[1:0] = 11), DD Parameter Analog Inputs ADC Input Voltage Range Absolute Pin Voltage with respect to GND Sampling Capacitance (C8051F912/11/02/01) Input Multiplexer Impedance ...
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C8051F91x-C8051F90x Table 4.12. Voltage Reference Electrical Characteristics V – = 1 +85 °C unless otherwise specified. DD Parameter Internal High Speed Reference (REFSL[1:0] = 11) Output Voltage VREF Turn-on Time Supply Current Internal Precision Reference ...
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Table 4.13. IREF0 Electrical Characteristics V – = 1 +85 °C, unless otherwise specified. DD Parameter Static Performance 1 Resolution Output Compliance Range Integral Nonlinearity Differential Nonlinearity Offset Error 2 Full Scale Error Absolute Current ...
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C8051F91x-C8051F90x Table 4.14. Comparator Electrical Characteristics V = 1.8 to 3.6 V, –40 to +85 °C unless otherwise noted. DD Parameter Response Time: * Mode 2 1 Response Time: * Mode ...
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Table 4.14. Comparator Electrical Characteristics (Continued 1.8 to 3.6 V, –40 to +85 °C unless otherwise noted. DD Parameter Hysteresis Mode 0 Hysteresis 1 Hysteresis 2 Hysteresis 3 Hysteresis 4 Mode 1 Hysteresis 1 Hysteresis 2 Hysteresis 3 ...
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C8051F91x-C8051F90x Table 4.16. DC-DC Converter (DC0) Electrical Characteristics –40 to +85 °C unless otherwise specified. VBAT = 0.9 to 1.8 V, Parameter Input Voltage Range Input Inductor Value Input Inductor Current Rat- ing Inductor DC Resistance Input Capacitor Value Output ...
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SAR ADC with 16-bit Auto-Averaging Accumulator and Autonomous Low Power Burst Mode The ADC0 on C8051F91x-C8051F90x devices is a 300 ksps, 10-bit or 75 ksps, 12-bit (‘F912/02 only) successive-approximation-register (SAR) ADC with integrated track-and-hold and programmable window detector. ADC0 ...
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C8051F91x-C8051F90x 5.1. Output Code Formatting The registers ADC0H and ADC0L contain the high and low bytes of the output conversion code from the ADC at the completion of each conversion. Data can be right-justified or left-justified, depending on the setting ...
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Modes of Operation ADC0 has a maximum conversion speed of 300 ksps in 10-bit mode. The ADC0 conversion clock (SARCLK divided version of the system clock when Burst Mode is disabled (BURSTEN = 0 divided ...
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C8051F91x-C8051F90x 5.2.2. Tracking Modes Each ADC0 conversion must be preceded by a minimum tracking time in order for the converted result to be accurate. The minimum tracking time is given in Table 4.10. The AD0TM bit in register ADC0CN controls ...
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Burst Mode Burst Mode is a power saving feature that allows ADC0 to remain in a low power state between conversions. When Burst Mode is enabled, ADC0 wakes from a low power state, accumulates 16, 32, ...
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C8051F91x-C8051F90x 5.2.4. Settling Time Requirements A minimum amount of tracking time is required before each conversion can be performed, to allow the sampling capacitor voltage to settle. This tracking time is determined by the AMUX0 resistance, the ADC0 sampling capacitance, ...
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Gain Setting The ADC has gain settings of 1x and 0.5x mode, the full scale reading of the ADC is determined directly 0.5x mode, the full-scale reading of the ADC occurs when the ...
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C8051F91x-C8051F90x Table 5.1. Representative Conversion Times and Energy Consumption for the SAR ADC with 1.65 V High-Speed VREF 8 bit 8.17 Highest nominal SAR clock MHz frequency (24 Total number of conversion clocks required Total tracking time (min) ...
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SFR Definition 5.1. ADC0CN: ADC0 Control Bit 7 6 Name AD0EN BURSTEN AD0INT R/W R/W Type Reset 0 0 SFR Page = 0x0; SFR Address = 0xE8; bit-addressable ; Bit Name 7 AD0EN ADC0 Enable. 0: ADC0 Disabled (low-power shutdown). ...
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C8051F91x-C8051F90x SFR Definition 5.2. ADC0CF: ADC0 Configuration Bit 7 6 Name AD0SC[4:0] Type Reset 1 1 SFR Page = 0x0; SFR Address = 0xBC Bit Name 7:3 AD0SC[4:0] ADC0 SAR Conversion Clock Divider. SAR Conversion clock is derived from FCLK ...
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SFR Definition 5.3. ADC0AC: ADC0 Accumulator Configuration Bit 7 6 Name AD012BE AD0AE R/W W Type Reset 0 0 SFR Page = 0x0; SFR Address = 0xBA Bit Name 7 AD012BE ADC0 12-Bit Mode Enables 12-bit Mode. Only available on ...
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C8051F91x-C8051F90x SFR Definition 5.4. ADC0PWR: ADC0 Burst Mode Power-Up Time Bit 7 6 Name AD0LPM Type R Reset SFR Page = 0xF; SFR Address = 0xBA Bit Name 7 AD0LPM ADC0 Low Power Mode Enable. Enables Low ...
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SFR Definition 5.5. ADC0TK: ADC0 Burst Mode Track Time Bit 7 6 Name Reserved Type Reset SFR Page = 0xF; SFR Address = 0xBD Bit Name 7:6 Reserved Reserved. Read = 0b; Write = Must Write ...
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C8051F91x-C8051F90x SFR Definition 5.6. ADC0H: ADC0 Data Word High Byte Bit 7 6 Name Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xBE Bit Name Description 7:0 ADC0[15:8] ADC0 Data Word High Byte. Note: If Accumulator shifting ...
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Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADC0 output registers to user- programmed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt-driven system, saving code space ...
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C8051F91x-C8051F90x SFR Definition 5.10. ADC0LTH: ADC0 Less-Than High Byte Bit 7 6 Name Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xC6 Bit Name 7:0 AD0LT[15:8] ADC0 Less-Than High Byte. Most Significant Byte of the 16-bit Less-Than ...
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Window Detector In Single-Ended Mode Figure 5.5 shows two example ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). The input voltage can range from 0 to VREF x (1023/1024) with respect to GND, and is represented by a ...
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C8051F91x-C8051F90x 5.7. ADC0 Analog Multiplexer ADC0 on C8051F91x-C8051F90x has an analog multiplexer, referred to as AMUX0. AMUX0 selects the positive inputs to the single-ended ADC0. Any of the following may be selected as the positive input: Port I/O pins, the ...
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SFR Definition 5.12. ADC0MX: ADC0 Input Channel Select Bit 7 6 Name R R Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xBB Bit Name 7:5 Unused Unused. Read = 000b; Write = Don’t Care. 4:0 AD0MX ...
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C8051F91x-C8051F90x 5.8. Temperature Sensor An on-chip temperature sensor is included on the C8051F91x-C8051F90x which can be directly accessed via the ADC multiplexer in single-ended configuration. To use the ADC to measure the temperature sensor, the ADC mux channel should select ...
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Calibration The uncalibrated temperature sensor output is extremely linear and suitable for relative temperature mea- surements (see Table 4.11 for linearity specifications). For absolute temperature measurements, offset and/or gain calibration is recommended. Typically a 1-point (offset) calibration includes the ...
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C8051F91x-C8051F90x SFR Definition 5.13. TOFFH: ADC0 Data Word High Byte Bit 7 6 Name R R Type Varies Varies Varies Reset SFR Page = 0xF; SFR Address = 0x86 Bit Name 7:0 TOFF[9:2] Temperature Sensor Offset High Bits. Most Significant ...
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Voltage and Ground Reference Options The voltage reference MUX is configurable to use an externally connected voltage reference, one of two internal voltage references, or one of two power supply voltages (see Figure 5.10). The ground reference MUX allows ...
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C8051F91x-C8051F90x 5.10. External Voltage References To use an external voltage reference, REFSL[1:0] should be set to 00 and the internal 1.68 V precision ref- erence should be disabled by setting REFOE to 0. Bypass capacitors should be added as recommended ...
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SFR Definition 5.15. REF0CN: Voltage Reference Control Bit 7 6 Name REFGND R R Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xD1 Bit Name 7:6 Unused Unused. Read = 00b; Write = Don’t Care. 5 REFGND ...
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C8051F91x-C8051F90x 6. Programmable Current Reference (IREF0) C8051F91x-C8051F90x devices include an on-chip programmable current reference (source or sink) with two output current settings: Low Power Mode and High Current Mode. The maximum current output in Low Power Mode is 63 µA ...
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SFR Definition 6.2. IREF0CF: Current Reference Configuration Bit 7 6 Name PWMEN Type R/W R/W Reset 0 0 SFR Page = 0xF; SFR Address = 0xB9 Bit Name 7 PWMEN PWM Enhanced Mode Enable. Enables the PWM Enhanced Mode. Only ...
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C8051F91x-C8051F90x 7. Comparators C8051F91x-C8051F90x devices include two on-chip programmable voltage comparators: Comparator 0 (CPT0) is shown in Figure 7.1; Comparator 1 (CPT1) is shown in Figure 7.2. The two comparators operate identically, but may differ in their ability to be ...
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Comparator Outputs When a comparator is enabled, its output is a logic 1 if the voltage at the positive input is higher than the voltage at the negative input. When disabled, the comparator output is a logic 0. The ...
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C8051F91x-C8051F90x 7.3. Comparator Response Time Comparator response time may be configured in software via the CPTnMD registers described on “CPT0MD: Comparator 0 Mode Selection” on page 92 and “CPT1MD: Comparator 1 Mode Selection” on page 94. Four response time settings ...
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Comparator Register Descriptions The SFRs used to enable and configure the comparators are described in the following register descriptions. A Comparator must be enabled by setting the CPnEN bit to logic 1 before it can be used. From an ...
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C8051F91x-C8051F90x SFR Definition 7.2. CPT0MD: Comparator 0 Mode Selection Bit 7 6 Name CP0RIE Type R/W R Reset 1 0 SFR Page = All Pages; SFR Address = 0x9D Bit Name 7 Reserved Reserved. Read = 1b, Must Write 1b. ...
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SFR Definition 7.3. CPT1CN: Comparator 1 Control Bit 7 6 Name CP1EN CP1OUT CP1RIF Type R/W R Reset 0 0 SFR Page= 0x0; SFR Address = 0x9A Bit Name 7 CP1EN Comparator1 Enable Bit. 0: Comparator1 Disabled. 1: Comparator1 Enabled. ...
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C8051F91x-C8051F90x SFR Definition 7.4. CPT1MD: Comparator 1 Mode Selection Bit 7 6 Name CP1RIE Type R/W R Reset 1 0 SFR Page = 0x0; SFR Address = 0x9C Bit Name 7 Reserved Reserved. Read = 1b, Must Write 1b. 6 ...
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Comparator0 and Comparator1 Analog Multiplexers Comparator0 and Comparator1 on C8051F91x-C8051F90x devices have analog input multiplexers to connect Port I/O pins and internal signals the comparator inputs; CP0+/CP0- are the positive and negative input multiplexers for Comparator0 and CP1+/CP1- are ...
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C8051F91x-C8051F90x SFR Definition 7.5. CPT0MX: Comparator0 Input Channel Select Bit 7 6 Name CMX0N[3:0] R/W R/W Type 1 1 Reset SFR Page = 0x0; SFR Address = 0x9F Bit Name 7:4 CMX0N Comparator0 Negative Input Selection. Selects the negative input ...
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SFR Definition 7.6. CPT1MX: Comparator1 Input Channel Select Bit 7 6 Name CMX1N[3:0] R/W R/W Type 1 1 Reset SFR Page = 0x0; SFR Address = 0x9E Bit Name 7:4 CMX1N Comparator1 Negative Input Selection. Selects the negative input channel ...
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C8051F91x-C8051F90x 8. CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The MCU family has a superset ...
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With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execution time. Clocks ...
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C8051F91x-C8051F90x Table 8.1. CIP-51 Instruction Set Summary Mnemonic ADD A, Rn Add register to A ADD A, direct Add direct byte to A ADD A, @Ri Add indirect RAM to A ADD A, #data Add immediate to A ADDC A, ...
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Table 8.1. CIP-51 Instruction Set Summary (Continued) Mnemonic CLR A Clear A CPL A Complement Rotate A left RLC A Rotate A left through Carry RR A Rotate A right RRC A Rotate A right through Carry ...
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C8051F91x-C8051F90x Table 8.1. CIP-51 Instruction Set Summary (Continued) Mnemonic ANL C, /bit AND complement of direct bit to Carry ORL C, bit OR direct bit to carry ORL C, /bit OR complement of direct bit to Carry MOV C, bit ...
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Notes on Registers, Operands and Addressing Modes: Rn—Register R0–R7 of the currently selected register bank. @Ri—Data RAM location addressed indirectly through R0 or R1. rel—8-bit, signed (twos complement) offset relative to the first byte of the following instruction. Used by ...
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C8051F91x-C8051F90x 8.4. CIP-51 Register Descriptions Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should not be set to logic l. Future product versions may use these bits to implement new features in ...
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SFR Definition 8.3. SP: Stack Pointer Bit 7 6 Name Type Reset 0 0 SFR Page = All Pages; SFR Address = 0x81 Bit Name 7:0 SP[7:0] Stack Pointer. The Stack Pointer holds the location of the top of the ...
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C8051F91x-C8051F90x SFR Definition 8.6. PSW: Program Status Word Bit 7 6 Name CY AC Type R/W R/W Reset 0 0 SFR Page = All Pages; SFR Address = 0xD0; Bit-Addressable Bit Name 7 CY Carry Flag. This bit is set ...
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Memory Organization The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory spaces: program memory and data memory. Program and data memory share the same address space but ...
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C8051F91x-C8051F90x 9.1. Program Memory The CIP-51 core has program memory space. The C8051F91x-C8051F90x devices implement 16 kB (C8051F912/ (C8051F902/1) of this program memory space as in-system, re- programmable Flash memory, organized in a contiguous ...
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CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the upper 128 bytes of data memory. Figure ...
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C8051F91x-C8051F90x 9.2.1.3. Stack A programmer's stack can be located anywhere in the 256-byte data memory. The stack area is designated using the Stack Pointer (SP) SFR. The SP will point to the last location used. The next value pushed on ...
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On-Chip XRAM The C8051F91x-C8051F90x MCUs include on-chip RAM mapped into the external data memory space (XRAM). The external memory space may be accessed using the external move instruction (MOVX) with the target address specified in either the data pointer ...
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C8051F91x-C8051F90x 10.2. Special Function Registers The special function register used for configuring XRAM access is EMI0CN. SFR Definition 10.1. EMI0CN: External Memory Interface Control Bit 7 6 Name Type R/W R/W Reset 0 0 SFR Page = 0x0; SFR Address ...
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Special Function Registers The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control and data exchange with the C8051F91x-C8051F90x's resources and peripherals. The CIP-51 controller core duplicates the SFRs found ...
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C8051F91x-C8051F90x 11.1. SFR Paging To accommodate more than 128 SFRs in the 0x80 to 0xFF address space, SFR paging has been implemented. By default, all SFR accesses target SFR Page 0x0 to allow access to the registers listed in Table ...
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SFR Definition 11.1. SFR Page: SFR Page Bit 7 6 Name Type Reset 0 0 SFR Page = All Pages; SFR Address = 0xA7 Bit Name 7:0 SFRPAGE[7:0] SFR Page. Specifies the SFR Page used when reading, writing, or modifying ...
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C8051F91x-C8051F90x Table 11.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. SFRs highlighted in blue are only available on ‘F912 and ‘F902 devices. Register Address SFR Page CPT1MD 0x9C 0x0 CPT1MX 0x9E ...
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Table 11.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. SFRs highlighted in blue are only available on ‘F912 and ‘F902 devices. Register Address SFR Page P0MDOUT 0xA4 0x0 P0SKIP 0xD4 0x0 ...
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C8051F91x-C8051F90x Table 11.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. SFRs highlighted in blue are only available on ‘F912 and ‘F902 devices. Register Address SFR Page PCA0MD 0xD9 0x0 PCA0PWM 0xDF ...
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Table 11.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. SFRs highlighted in blue are only available on ‘F912 and ‘F902 devices. Register Address SFR Page TL0 0x8A 0x0 TL1 0x8B 0x0 ...
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C8051F91x-C8051F90x 12. Interrupt Handler The C8051F91x-C8051F90x microcontroller family includes an extended interrupt system supporting multiple interrupt sources and two priority levels. The allocation of interrupt sources between on-chip peripherals and external input pins varies according to the specific version of ...
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Interrupt Priorities Each interrupt source can be individually programmed to one of two priority levels: low or high. A low priority interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be preempted. ...
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C8051F91x-C8051F90x Table 12.1. Interrupt Summary Interrupt Interrupt Source Vector 0x0000 Reset 0x0003 External Interrupt 0 (INT0) Timer 0 Overflow 0x000B 0x0013 External Interrupt 1 (INT1) Timer 1 Overflow 0x001B UART0 0x0023 Timer 2 Overflow 0x002B SPI0 0x0033 SMB0 0x003B SmaRTClock ...
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Interrupt Register Descriptions The SFRs used to enable the interrupt sources and set their priority level are described in the following register descriptions. Refer to the data sheet section associated with a particular on-chip peripheral for information regarding valid ...
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C8051F91x-C8051F90x SFR Definition 12.1. IE: Interrupt Enable Bit 7 6 Name EA ESPI0 Type R/W R/W Reset 0 0 SFR Page = All Pages; SFR Address = 0xA8; Bit-Addressable Bit Name 7 EA Enable All Interrupts. Globally enables/disables all interrupts. ...
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SFR Definition 12.2. IP: Interrupt Priority Bit 7 6 PSPI0 Name Type R R/W Reset 1 0 SFR Page = 0x0; SFR Address = 0xB8; Bit-Addressable Bit Name 7 Unused Unused. Read = 1b, Write = don't care. 6 PSPI0 ...
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C8051F91x-C8051F90x SFR Definition 12.3. EIE1: Extended Interrupt Enable 1 Bit 7 6 Name ET3 ECP1 Type R/W R/W Reset 0 0 SFR Page = All Pages; SFR Address = 0xE6 Bit Name 7 ET3 Enable Timer 3 Interrupt. This bit ...
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SFR Definition 12.4. EIP1: Extended Interrupt Priority 1 Bit 7 6 Name PT3 PCP1 Type R/W R/W Reset 0 0 SFR Page = All Pages; SFR Address = 0xF6 Bit Name 7 PT3 Timer 3 Interrupt Priority Control. This bit ...
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C8051F91x-C8051F90x SFR Definition 12.5. EIE2: Extended Interrupt Enable 2 Bit 7 6 Name R/W R/W Type Reset 0 0 SFR Page = All Pages;SFR Address = 0xE7 Bit Name 7:4 Unused Unused. Read = 0000b. Write = Don’t care. 3 ...
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SFR Definition 12.6. EIP2: Extended Interrupt Priority 2 Bit 7 6 Name R R Type Reset 0 0 SFR Page = All Pages; SFR Address = 0xF7 Bit Name 7:4 Unused Unused. Read = 0000b. Write = Don’t care. 3 ...
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C8051F91x-C8051F90x 12.6. External Interrupts INT0 and INT1 The INT0 and INT1 external interrupt sources are configurable as active high or low, edge or level sensitive. The IN0PL (INT0 Polarity) and IN1PL (INT1 Polarity) bits in the IT01CF register select active ...
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SFR Definition 12.7. IT01CF: INT0/INT1 Configuration Bit 7 6 Name IN1PL IN1SL[2:0] Type R/W Reset 0 0 SFR Page = 0x0; SFR Address = 0xE4 Bit Name 7 IN1PL INT1 Polarity. 0: INT1 input is active low. 1: INT1 input ...
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C8051F91x-C8051F90x 13. Flash Memory On-chip, re-programmable Flash memory is included for program code and non-volatile data storage. The Flash memory can be programmed in-system through the C2 interface or by software using the MOVX write instruction. Once cleared to logic ...
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Flash Erase Procedure The Flash memory is organized in 512-byte pages. The erase operation applies to an entire page (setting all bytes in the page to 0xFF). To erase an entire Flash page, perform the following steps: 1. Save ...
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C8051F91x-C8051F90x 13.3. Security Options The CIP-51 provides security options to protect the Flash memory from inadvertent modification by software as well as to prevent the viewing of proprietary program code and constants. The Program Store Write Enable (bit PSWE in ...
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Table 13.1. Flash Security Summary Action Read, Write or Erase unlocked pages (except page with Lock Byte) Read, Write or Erase locked pages (except page with Lock Byte) Read or Write page containing Lock Byte (if no pages are locked) ...
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... The part number can be determined by reading the value of the Flash byte at address 0x3FFE. The value of the Flash byte at address 0x3FFE can be decoded as follows: 0xD0—C8051F901 0xD1—C8051F902 0xD2—C8051F911 0xD3—C8051F912 136 ...
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Flash Write and Erase Guidelines Any system which contains routines which write or erase Flash memory from software involves some risk that the write or erase routines will execute unintentionally if the CPU is operating outside its specified operating ...
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C8051F91x-C8051F90x 13.5.2. PSWE Maintenance 7. Reduce the number of places in code where the PSWE bit (b0 in PSCTL) is set There should be exactly one routine in code that sets PSWE write ...
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Minimizing Flash Read Current The Flash memory in the C8051F91x-C8051F90x devices is responsible for a substantial portion of the total digital supply current when the device is executing code. Below are suggestions to minimize Flash read current. 1. Use ...
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C8051F91x-C8051F90x SFR Definition 13.1. PSCTL: Program Store R/W Control Bit 7 6 Name Type R R Reset 0 0 SFR Page =0x0; SFR Address = 0x8F Bit Name 7:3 Unused Unused. Read = 00000b, Write = don’t care. 2 SFLE ...
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SFR Definition 13.2. FLKEY: Flash Lock and Key Bit 7 6 Name Type Reset 0 0 SFR Page = 0x0; SFR Address = 0xB6 Bit Name 7:0 FLKEY[7:0] Flash Lock and Key Register. Write: This register provides a lock and ...
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C8051F91x-C8051F90x SFR Definition 13.3. FLSCL: Flash Scale Bit 7 6 Name BYPASS Type R R/W Reset 0 0 SFR Page = 0x0; SFR Address = 0xB6 Bit Name 7 Reserved Reserved. Always Write BYPASS Flash Read Timing ...
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Power Management C8051F91x-C8051F90x devices support 5 power modes: Normal, Idle, Stop, Suspend, and Sleep. The power management unit (PMU0) allows the device to enter and wake-up from the available power modes. A brief description of each power mode is ...
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C8051F91x-C8051F90x 14.1. Normal Mode The MCU is fully functional in normal mode. Figure 14.1 shows the on-chip power distribution to various peripherals. There are three supply voltages powering various sections of the chip: VBAT, VDD/DC+, and the 1.8 V internal ...
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Idle Mode Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon as the instruction that sets the bit completes execution. All internal registers and memory maintain their original ...
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C8051F91x-C8051F90x 14.4. Suspend Mode Setting the Suspend Mode Select bit (PMU0CF.6) causes the system clock to be gated off and all internal oscillators disabled. The system clock source must be set to the low power internal oscillator or the preci- ...
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Note: By default, the VDD/DC+ supply is connected to VBAT upon entry into Sleep Mode (one-cell mode). If the VDDSLP bit (DC0CF.1) is set to logic 1, the VDD/DC+ supply will float in Sleep Mode. This allows the decoupling capacitance ...
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C8051F91x-C8051F90x 14.7. Determining the Event that Caused the Last Wakeup When waking from idle mode, the CPU will vector to the interrupt which caused it to wake up. When wak- ing from stop mode, the RSTSRC register may be read ...
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SFR Definition 14.1. PMU0CF: Power Management Unit Configuration Bit 7 6 SLEEP SUSPEND CLEAR Name W W Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xB5 Bit Name Description 7 SLEEP Sleep Mode Select 6 SUSPEND Suspend ...
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C8051F91x-C8051F90x SFR Definition 14.2. PMU0MD: Power Management Unit Mode Bit 7 6 RTCOE WAKEOE MONDIS Name R/W R/W Type 0 0 Reset SFR Page = 0xF; SFR Address = 0xB5 Bit Name 7 RTCOE Buffered SmaRTClock Output Enable. Enables the ...
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SFR Definition 14.3. PCON: Power Management Control Register Bit 7 6 Name Type 0 0 Reset SFR Page = All Pages; SFR Address = 0x87 Bit Name Description 7:2 GF[5:0] General Purpose Flags 1 STOP Stop Mode Select 0 IDLE ...
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C8051F91x-C8051F90x 15. Cyclic Redundancy Check Unit (CRC0) C8051F91x-C8051F90x devices include a cyclic redundancy check unit (CRC0) that can perform a CRC using a 16-bit or 32-bit polynomial. CRC0 accepts a stream of 8-bit data written to the CRC0IN register. CRC0 ...
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CRC_acc = CRC_acc ^ (CRC_input << 8); // "Divide" the poly into the dividend using CRC XOR subtraction // CRC_acc holds the "remainder" of each divide // // Only complete this division for 8 bits since ...
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C8051F91x-C8051F90x 15.2. Preparing for a CRC Calculation To prepare CRC0 for a CRC calculation, software should select the desired polynomial and set the initial value of the result. Two polynomials are available: 0x1021 (16-bit) and 0x04C11DB7 (32-bit). The CRC0 result ...
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SFR Definition 15.1. CRC0CN: CRC0 Control Bit 7 6 Name R/W R/W Type 0 0 Reset SFR Page = 0xF; SFR Address = 0x92 Bit Name 7:5 Unused Unused. Read = 000b; Write = Don’t Care. 4 CRC0SEL CRC0 Polynomial ...
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C8051F91x-C8051F90x SFR Definition 15.2. CRC0IN: CRC0 Data Input Bit 7 6 Name Type Reset 0 0 SFR Page = 0xF; SFR Address = 0x93 Bit Name 7:0 CRC0IN[7:0] CRC0 Data Input. Each write to CRC0IN results in the written data ...
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SFR Definition 15.4. CRC0AUTO: CRC0 Automatic Control Bit 7 6 Name AUTOEN CRCDONE Type Reset 0 1 SFR Page = 0xF; SFR Address = 0x96 Bit Name 7 AUTOEN Automatic CRC Calculation Enable. When AUTOEN is set to 1, any ...
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C8051F91x-C8051F90x SFR Definition 15.5. CRC0CNT: CRC0 Automatic Flash Sector Count Bit 7 6 Name Type Reset 0 0 SFR Page = 0xF; SFR Address = 0x97 Bit Name 7:6 Unused Unused. Read = 00b; Write = Don’t Care. 5:0 CRC0CNT[5:0] ...
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CRC0 Bit Reverse Feature CRC0 includes hardware to reverse the bit order of each bit in a byte as shown in Figure 15.2. Each byte of data written to CRC0FLIP is read back bit reversed. For example, if 0xC0 ...
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C8051F91x-C8051F90x 16. On-Chip DC-DC Converter (DC0) C8051F91x-C8051F90x devices include an on-chip dc-dc converter to allow operation from a single cell battery with a supply voltage as low as 0.9 V. The dc-dc converter is a switching boost converter with an ...
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Startup Behavior On initial power-on, the dc-dc converter outputs a constant 50% duty cycle until there is sufficient voltage on the output capacitor to maintain regulation. The size of the output capacitor and the amount of load cur- rent ...
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C8051F91x-C8051F90x 16.2. High Power Applications The dc-dc converter is designed to provide the system with output power, however, it can safely provide up to 100 mW of output power without any risk of damage to the device. ...
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Enabling the DC-DC Converter On power-on reset, the state of the DCEN pin is sampled to determine if the device will power up in one- cell or two-cell mode. In two-cell mode, the dc-dc converter always remains disabled. In ...
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C8051F91x-C8051F90x 16.5. Minimizing Power Supply Noise To minimize noise on the power supply lines, the GND and GND/DC- pins should be kept separate, as shown in Figure 16.2; one or the other should be connected to the pc board ground ...
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VDD/DC+ output can be made to float during Sleep mode by setting the VDDSLP bit in the DC0CF register to 1. Setting this bit can provide power savings in two ways. First, if the ...
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C8051F91x-C8051F90x 16.11. Passive Diode Mode (C8051F912/02 only) Setting the EXTDEN bit in DC0MD enables the Passive Diode Mode. In this mode, the control circuits for the Diode Bypass switch are disabled, which reduces the converter’s quiescent operating current. An external ...
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DC-DC Converter Register Descriptions The SFRs used to configure the dc-dc converter are described in the following register descriptions. The reset values for these registers can be used as-is in most systems; therefore, no software intervention or initialization is ...
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C8051F91x-C8051F90x SFR Definition 16.2. DC0CF: DC-DC Converter Configuration Bit 7 6 Name LPEN CLKDIV[1:0] Type R/W R/W Reset 0 0 SFR Page = 0x0; SFR Address = 0x96 Bit Name 7 LPEN Low Power Mode Enable. Enables the dc-dc low ...
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SFR Definition 16.3. DC0MD: DC-DC Mode Bit 7 6 Name Type R/W R/W Reset 0 0 SFR Page = 0xF; SFR Address = 0x94 Bit Name 7:4 Unused Unused. Read = 0000b, Write = don’t care. 3 BYPFLG Bypass Indicator. ...
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C8051F91x-C8051F90x 17. Voltage Regulator (VREG0) C8051F91x-C8051F90x devices include an internal voltage regulator (VREG0) to regulate the internal core supply to 1.8 V from a VDD/DC+ supply of 1.8 to 3.6 V. Electrical characteristics for the on-chip regulator are specified in ...
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Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: • CIP-51 halts program execution • Special Function Registers (SFRs) are initialized to their ...
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C8051F91x-C8051F90x 18.1. Power-On (VBAT Supply Monitor) Reset During power-up, the device is held in a reset state and the RST pin is driven low until additional delay occurs before the device is released from reset; the ...
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Power-Fail (VDD/DC+ Supply Monitor) Reset C8051F91x-C8051F90x devices have a VDD/DC+ Supply Monitor that is enabled and selected as a reset source after each power-on or power-fail reset. When enabled and selected as a reset source, any power down transition ...
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C8051F91x-C8051F90x Important Notes: • The Power-on Reset (POR) delay is not incurred after a VDD/DC+ supply monitor reset. See Section “4. Electrical Characteristics” on page 36 for complete electrical characteristics of the VDD/DC+ moni- tor. • Software should take care ...
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SFR Definition 18.1. VDM0CN: VDD/DC+ Supply Monitor Control Bit 7 6 Name VDMEN VDDSTAT VDDOK R/W R Type 1 Varies Varies Reset SFR Page = 0x0; SFR Address = 0xFF Bit Name 7 VDMEN VDD/DC+ Supply Monitor Enable. This bit ...
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C8051F91x-C8051F90x 18.3. External Reset The external RST pin provides a means for external circuitry to force the device into a reset state. Asserting an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the ...
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Flash Error Reset If a Flash read/write/erase or program read targets an illegal address, a system reset is generated. This may occur due to any of the following: • A Flash write or erase is attempted above user code ...
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C8051F91x-C8051F90x SFR Definition 18.2. RSTSRC: Reset Source Bit 7 6 Name RTC0RE FERROR C0RSEF R/W R Type Varies Varies Varies Reset SFR Page = 0x0; SFR Address = 0xEF. Bit Name Description 7 RTC0RE SmaRTClock Reset Enable and Flag 6 ...
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Clocking Sources C8051F91x-C8051F90x devices include a programmable precision internal oscillator, an external oscillator drive circuit, a low power internal oscillator, and a SmaRTClock real time clock oscillator. The precision internal oscillator can be enabled/disabled and calibrated using the OSCICN ...
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C8051F91x-C8051F90x 19.1. Programmable Precision Internal Oscillator All C8051F91x-C8051F90x devices include a programmable precision internal oscillator that may be selected as the system clock. OSCICL is factory calibrated to obtain a 24.5 MHz frequency. See Section “4. Electrical Characteristics” on page ...
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MHz 15 pF Figure 19.2. 25 MHz External Crystal Example Important Note on External Crystals: Crystal oscillator circuits are quite sensitive to PCB layout. The crystal should be placed as close as possible to the XTAL pins ...
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C8051F91x-C8051F90x 19.3.2. External RC Mode network is used as the external oscillator, the circuit should be configured as shown in Figure 19.1, Option 2. The RC network should be added to XTAL2, and XTAL2 should be configured ...
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When the RC oscillator is first enabled, the external oscillator valid detector allows software to determine when oscillation has stabilized. The recommended procedure for starting the RC oscillator is as follows: 1. Configure XTAL2 for analog I/O and disable the ...
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C8051F91x-C8051F90x 19.3.4. External CMOS Clock Mode If an external CMOS clock is used as the external oscillator, the clock should be directly routed into XTAL2. The XTAL2 pin should be configured as a digital input. XTAL1 is not used in ...
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Special Function Registers for Selecting and Configuring the System Clock The clocking sources on C8051F91x-C8051F90x devices are enabled and configured using the OSCICN, OSCICL, OSCXCN and the SmaRTClock internal registers. See Section “20. SmaRTClock (Real Time Clock)” on page ...
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C8051F91x-C8051F90x SFR Definition 19.2. OSCICN: Internal Oscillator Control Bit 7 6 Name IOSCEN IFRDY R/W R Type 0 0 Varies Reset SFR Page = 0x0; SFR Address = 0xB2 Bit Name 7 IOSCEN Internal Oscillator Enable. 0: Internal oscillator disabled. ...
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SFR Definition 19.4. OSCXCN: External Oscillator Control Bit 7 6 Name XCLKVLD XOSCMD[2: Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xB1 Bit Name 7 XCLKVLD External Oscillator Valid Flag. Provides External Oscillator status and ...
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C8051F91x-C8051F90x 20. SmaRTClock (Real Time Clock) C8051F91x-C8051F90x devices include an ultra low power 32-bit SmaRTClock Peripheral (Real Time Clock) with alarm. The SmaRTClock has a dedicated 32 kHz oscillator that can be configured for use with or without a crystal. ...
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SmaRTClock Interface The SmaRTClock Interface consists of three registers: RTC0KEY, RTC0ADR, and RTC0DAT. These interface registers are located on the CIP-51’s SFR map and provide access to the SmaRTClock internal registers listed in Table 20.1. The SmaRTClock internal registers ...
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C8051F91x-C8051F90x 20.1.2. Using RTC0ADR and RTC0DAT to Access SmaRTClock Internal Registers The SmaRTClock internal registers can be read and written using RTC0ADR and RTC0DAT. The RTC0ADR register selects the SmaRTClock internal register that will be targeted by subsequent reads or ...
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RTC0ADR Autoincrement Feature For ease of reading and writing the 32-bit CAPTURE and ALARM values, RTC0ADR automatically increments after each read or write to a CAPTUREn or ALARMn register. This speeds up the process of setting an alarm or ...
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C8051F91x-C8051F90x SFR Definition 20.1. RTC0KEY: SmaRTClock Lock and Key Bit 7 6 Name Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xAE Bit Name 7:0 RTC0ST SmaRTClock Interface Lock/Key and Status. Locks/unlocks the SmaRTClock interface when written. ...
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SFR Definition 20.2. RTC0ADR: SmaRTClock Address Bit 7 6 Name BUSY AUTORD R/W R/W Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xAC Bit Name 7 BUSY SmaRTClock Interface Busy Indicator. Indicates SmaRTClock interface status. Writing 1 ...
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C8051F91x-C8051F90x 20.2. SmaRTClock Clocking Sources The SmaRTClock peripheral is clocked from its own timebase, independent of the system clock. The SmaRTClock timebase can be derived from an external CMOS clock, the internal LFO (‘F912 and ‘F902 devices only), or the ...
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Using the SmaRTClock Oscillator in Self-Oscillate Mode When using Self-Oscillate Mode, the XTAL3 and XTAL4 pins should be shorted together. The RTC0PIN register can be used to internally short XTAL3 and XTAL4. The following steps show how to configure ...
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C8051F91x-C8051F90x 20.2.4. Programmable Load Capacitance The programmable load capacitance has 16 values to support crystal oscillators with a wide range of recommended load capacitance. If Automatic Load Capacitance Stepping is enabled, the crystal load capacitors start at the smallest setting ...
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Automatic Gain Control (Crystal Mode Only) and SmaRTClock Bias Doubling Automatic Gain Control allows the SmaRTClock oscillator to trim the oscillation amplitude of a crystal in order to achieve the lowest possible power consumption. Automatic Gain Control automatically detects ...
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C8051F91x-C8051F90x . Table 20.3. SmaRTClock Bias Settings Mode Crystal Self-Oscillate 198 Setting Power Consumption Bias Double Off, AGC On Lowest 600 nA Bias Double Off, AGC Off Low 800 nA Bias Double On, AGC On High Bias Double On, AGC ...
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Missing SmaRTClock Detector The missing SmaRTClock detector is a one-shot circuit enabled by setting MCLKEN (RTC0CN. When the SmaRTClock Missing Clock Detector is enabled, OSCFAIL (RTC0CN.5) is set by hardware if SmaRTClock oscillator remains high or low ...
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C8051F91x-C8051F90x 20.3.2. Setting a SmaRTClock Alarm The SmaRTClock alarm function compares the 32-bit value of SmaRTClock Timer to the value of the ALARMn registers. An alarm event is triggered if the SmaRTClock timer is equal to the ALARMn registers. If ...