C8051F901-GU Silicon Laboratories Inc, C8051F901-GU Datasheet - Page 315

IC MCU 8BIT 8KB FLASH 24QSOP

C8051F901-GU

Manufacturer Part Number
C8051F901-GU
Description
IC MCU 8BIT 8KB FLASH 24QSOP
Manufacturer
Silicon Laboratories Inc
Series
C8051F9xxr
Datasheets

Specifications of C8051F901-GU

Program Memory Type
FLASH
Program Memory Size
8KB (8K x 8)
Package / Case
24-QSOP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 3.6 V
Data Converters
A/D 15x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F9x
Core
8051
Data Ram Size
768 B
Interface Type
UART
Maximum Clock Frequency
25 MHz
Number Of Timers
4
Operating Supply Voltage
0.9 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F912DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Package
24QSOP
Device Core
8051
Family Name
C8051F90x
Maximum Speed
25 MHz
Data Bus Width
8 Bit
Number Of Programmable I/os
16
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1847-5

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F901-GU
Manufacturer:
Silicon Laboratories Inc
Quantity:
135
27.2. C2 Pin Sharing
The C2 protocol allows the C2 pins to be shared with user functions so that in-system debugging and
Flash programming may be performed. This is possible because C2 communication is typically performed
when the device is in the halt state, where all on-chip peripherals and user software are stalled. In this
halted state, the C2 interface can safely “borrow” the C2CK (RST) and C2D pins. In most applications,
external resistors are required to isolate C2 interface traffic from the user application. A typical isolation
configuration is shown in Figure 27.1.
The configuration in Figure 27.1 assumes the following:
Additional resistors may be necessary depending on the specific application.
1. The user input (b) cannot change state while the target device is halted.
2. The RST pin on the target device is used as an input only.
Output (c)
RST (a)
Input (b)
Figure 27.1. Typical C2 Pin Sharing
C2 Interface Master
Rev. 1.0
C8051F91x-C8051F90x
C2CK
C2D
C8051Fxxx
315

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