C8051F901-GU Silicon Laboratories Inc, C8051F901-GU Datasheet - Page 147

• Manufacturer Part Number: C8051F901-GU
• Description: IC MCU 8BIT 8KB FLASH 24QSOP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F9xxr

Specifications of C8051F901-GU

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 24-QSOP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 3.6 V
• Data Converters: A/D 15x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F9x
• Core: 8051
• Data Ram Size: 768 B
• Interface Type: UART
• Maximum Clock Frequency: 25 MHz
• Number Of Timers: 4
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F912DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Package: 24QSOP
• Device Core: 8051
• Family Name: C8051F90x
• Maximum Speed: 25 MHz
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1847-5

Note: By default, the VDD/DC+ supply is connected to VBAT upon entry into Sleep Mode (one-cell mode). If the
RAM and SFR register contents are preserved in sleep mode as long as the voltage on VBAT does not fall
below V
resume code execution upon waking up from Sleep mode. The following wake-up sources can be config-
ured to wake the device from sleep mode:




The Comparator0 Rising Edge wakeup is only valid in two-cell mode. The comparator requires a supply
voltage of at least 1.8 V to operate properly. On ‘F912 and ‘F902 devices, the VBAT supply monitor can be
disabled to save power by writing 1 to the MONDIS (PMU0MD.5) bit. When the VBAT supply monitor is
disabled, all reset sources will trigger a full POR and will re-enable the VBAT supply monitor.
In addition, any falling edge on RST (due to a pin reset or a noise glitch) will cause the device to exit sleep
mode. In order for the MCU to respond to the pin reset event, software must not place the device back into
sleep mode for a period of 15 µs. The PMU0CF register may be checked to determine if the wake-up was
due to a falling edge on the RST pin. If the wake-up source is not due to a falling edge on RST, there is no
time restriction on how soon software may place the device back into sleep mode. A 4.7 k pullup resistor
to VDD/DC+ is recommend for RST to prevent noise glitches from waking the device.
14.6. Configuring Wakeup Sources
Before placing the device in a low power mode, one or more wakeup sources should be enabled so that
the device does not remain in the low power mode indefinitely. For Idle Mode, this includes enabling any
interrupt. For Stop Mode, this includes enabling any reset source or relying on the RST pin to reset the
device.
Wake-up sources for suspend and sleep modes are configured through the PMU0CF register. Wake-up
sources are enabled by writing 1 to the corresponding wake-up source enable bit. Wake-up sources must
be re-enabled each time the device is placed in suspend or sleep mode, in the same write that places the
device in the low power mode.
The reset pin is always enabled as a wake-up source. On the falling edge of RST, the device will be
awaken from sleep mode. The device must remain awake for more than 15 µs in order for the reset to take
place.
SmaRTClock Oscillator Fail
SmaRTClock Alarm
Port Match Event
Comparator0 Rising Edge.
VDDSLP bit (DC0CF.1) is set to logic 1, the VDD/DC+ supply will float in Sleep Mode. This allows the
decoupling capacitance on the VDD/DC+ supply to maintain the supply rail until the capacitors are discharged.
For relatively short sleep intervals, this can result in substantial power savings because the decoupling
capacitance is not continuously charged and discharged.
POR
. The PC counter and all other volatile state information is preserved allowing the device to
Rev. 1.0
C8051F91x-C8051F90x
147