MC705P6ACDWE Freescale Semiconductor, MC705P6ACDWE Datasheet

IC MCU 176 BYTES RAM 28-SOIC

MC705P6ACDWE

Manufacturer Part Number
MC705P6ACDWE
Description
IC MCU 176 BYTES RAM 28-SOIC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC705P6ACDWE

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SIO
Peripherals
POR, WDT
Number Of I /o
21
Program Memory Size
4.5KB (4.5K x 8)
Program Memory Type
OTP
Ram Size
176 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
HC705P
Core
HC05
Data Bus Width
8 bit
Data Ram Size
176 B
Maximum Clock Frequency
2.1 MHz
Number Of Programmable I/os
21
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
MC68HC705P6A
Advance Information Data Sheet
This document contains certain information on a new product.Specifications and information herein are subject to change without notice.
MC68HC705P6A
Rev. 2.1
9/2005
M68HC05
Microcontrollers
freescale.com

MC705P6ACDWE Summary of contents

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MC68HC705P6A Advance Information Data Sheet M68HC05 Microcontrollers MC68HC705P6A Rev. 2.1 9/2005 freescale.com This document contains certain information on a new product.Specifications and information herein are subject to change without notice. ...

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... September, 2.1 Updated to meet Freescale identity guidelines. 2005 Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2005. All rights reserved. MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor Description Page Number(s) ...

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... Revision History MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 4 Freescale Semiconductor ...

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... Chapter 7 Serial Input/Output Port (SIOP .41 Chapter 8 Capture/Compare Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Chapter 9 Analog Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Chapter 10 EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Chapter 11 Mask Option Register (MOR Chapter 12 Central Processor Unit (CPU) Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Chapter 13 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Chapter 14 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Chapter 15 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Chapter 16 Ordering Information MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor 5 ...

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... List of Chapters MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 6 Freescale Semiconductor ...

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... Bootloader Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.4 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.4.1 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.4.1.1 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.4.1.2 Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.4.2 WAIT Instruction 3.5 COP Watchdog Timer Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor Chapter 1 General Description Chapter 2 Memory Chapter 3 Operating Modes . . . . . . . . . . . . . . . . 16 REFH 7 ...

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... Serial Data Output (SDO 7.3 SIOP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.3.1 SIOP Control Register (SCR 7.3.2 SIOP Status Register (SSR 7.3.3 SIOP Data Register (SDR MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 8 Chapter 4 Resets Chapter 5 Interrupts Chapter 6 Input/Output Ports Chapter 7 Serial Input/Output Port (SIOP) Freescale Semiconductor ...

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... EPROM Programming Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10.4 EPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10.5 EPROM Programming Register (EPROG 10.6 EPROM Bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.7 Programming from an External Memory Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor Chapter 8 Capture/Compare Timer Chapter 9 Analog Subsystem ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 REFH Chapter 10 EPROM Table of Contents 9 ...

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... Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 14.5 5.0-Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 14.6 3.3-Volt DC Electrical Charactertistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 14.7 A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 10 Chapter 11 Mask Option Register (MOR) Chapter 12 Central Processor Unit (CPU) Core Chapter 13 Instruction Set Chapter 14 Electrical Specifications Freescale Semiconductor ...

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... Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 15.2 Plastic Dual In-Line Package (Case 710 15.3 Small Outline Integrated Circuit Package (Case 751F 16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 16.2 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor Chapter 15 Mechanical Specifications Chapter 16 Ordering Information Table of Contents 11 ...

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... Table of Contents MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 12 Freescale Semiconductor ...

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... SIOP most significant bit (MSB) or least significant bit (LSB) first – SIOP clock rates: OSC divided by 8, 16, 32 – Stop instruction mode, STOP or HALT – EPROM security external lockout – Programmable keyscan (pullups/interrupts) on PA0–PA7 MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor Figure 1-1. 13 ...

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... STK PNTR NOTE Chapter 14 Electrical OSC 1 ÷2 OSC OSC 2 16-BIT TIMER ÷4 PD7/TCAP 1 INPUT CAPTURE TCMP 1 OUTPUT COMPARE PD5 PORT D LOGIC PC7/VR EFH PC6/AD0 PC5/AD1 PC4/AD2 PC3/AD3 PC2 PC1 PC0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Specifications. Freescale Semiconductor ...

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... The oscillator cannot be turned off by software unless the MOR bit, SWAIT clear when a STOP instruction is executed (or STOP) DD OSC1 4.7 MΩ (a) Crystal or Ceramic Resonator Connections MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor and connected to a regulated +5 volt supply and 1-2(a) Figure 1-2(a) Figure 1-2(b) MCU ...

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... It may be read at any time, regardless of which mode of operation the 16-bit timer is in. Refer to Chapter 6 Input/Output Ports and MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 16 Figure 1-2(b). Chapter 4 and Chapter 7 Serial Input/Output Port and Chapter 9 Analog Subsystem. Chapter 8 Capture/Compare Figure Resets. Chapter 6 Input/Output Ports. (SIOP). REFH Timer. Freescale Semiconductor 1-2(a) ...

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... Schmitt trigger to improve noise immunity. Refer to If the voltage level applied to the IRQ/V the MCU’s mode of operation. See MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor pin will trigger an interrupt on either a negative edge at PP pin is held in the low state. In either case, the IRQ/V PP time period ...

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... General Description MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 18 Freescale Semiconductor ...

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... There are 4608 bytes of user EPROM at locations $0100 through $12FF, plus 48 bytes in user page zero locations $0020 through $004F, and 16 additional bytes for user vectors at locations $1FF0 through $1FFF. The bootloader ROM and vectors are at locations $1F01 through $1FEF. MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor Figure 2-1. Figure 2-1 ...

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... TIMER VECTOR (HIGH BYTE) $1FF8 TIMER VECTOR (LOW BYTE) $1FF9 IRQ VECTOR (HIGH BYTE) $1FFA IRQ VECTOR (LOW BYTE) $1FFB SWI VECTOR (HIGH BYTE) $1FFC SWI VECTOR (LOW BYTE) $1FFD RESET VECTOR (HIGH BYTE) $1FFE RESET VECTOR (LOW BYTE) $1FFF Freescale Semiconductor ...

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... A/D CONVERTER CONTROL AND STATUS REGISTER Figure 2-2. MC68HC705P6A I/O and Control MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor PORT A DATA REGISTER PORT B DATA REGISTER PORT C DATA REGISTER PORT D DATA REGISTER PORT A DATA DIRECTION REGISTER PORT B DATA DIRECTION REGISTER ...

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... DDRC7 DDRC6 DDRC5 DDRC4 DDRD5 SPE MSTR SPIF DCOL SDR7 SDR6 SDR5 SDR4 Unaffected by reset = Unimplemented Bit 0 PA3 PA2 PA1 PA0 PC3 PC2 PC1 PC0 DDRA3 DDRA2 DDRA1 DDRA0 DDRC3 DDRC2 DDRC1 DDRC0 SDR3 SSDR2 SDR1 SDR0 = Reserved U = Undetermined Freescale Semiconductor ...

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... Timer Register LSB (TRL) $0019 Write: See page 49. Reset: Read: Alternate Timer $001A Register MSB (ATRH) Write: See page 49. Reset: Figure 2-3. I/O and Control Register Summary (Sheet MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor Bit ICIE OCIE TOIE 0 ...

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... SPR0 Unimplemented Figure 2-4. Mask Option Register (MOR ACRL4 ACRL3 ACRL2 ACRL1 ELAT AD4 AD3 AD2 AD1 Unaffected by reset 0 0 CH2 CH1 Reserved U = Undetermined Bit 0 PA2PU PA1PU PA0PU Bit 0 LSBF LEVEL COP Freescale Semiconductor Bit 0 ACRL0 0 EPGM 0 AD0 CH0 0 R for ...

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... The computer operating properly (COP) watchdog timer is located at address $1FF0. Writing a logical 0 to bit zero of this location will clear the COP watchdog counter as described in Properly (COP) Reset. $1FF0 Bit 7 Read: 0 Write: Reset: 0 Figure 2-5. COP Watchdog Timer Location MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor Computer Operating Properly (COP) Clear Register ...

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... Memory MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 26 Freescale Semiconductor ...

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... PD7/TCAP pin. The user code in the external memory device must have data located DD in the same address space it will occupy in the internal MCU EPROM, including the mask option register (MOR) at $1EFF and $1F00. MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor IRQ/V PD7/TCAP PP V ...

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... OSC2 25 PA6 4 PD7/TCAP PA5 5 24 TCMP PA4 6 23 PD5 22 PA3 7 PC0 PA2 21 8 PC1 PA1 9 20 PC2 19 PA0 10 PC3/AD3 18 SDO/PB5 11 PC4/AD2 SDI/PB6 12 17 PC5/AD1 16 SCK/PB7 13 PC6/AD0 PC7/V SS Figure 3-1. User Mode Pinout NOTE for additional information. DD REFH 3.5 COP Freescale Semiconductor ...

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... EXTERNAL RESET? N IRQ Y EXTERNAL INTERRUPT? RESTART EXTERNAL OSCILLATOR, N START STABILIZATION DELAY OF STABILIZATION DELAY? N MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor HALT EXTERNAL OSCILLATOR ACTIVE AND INTERNAL TIMER CLOCK ACTIVE STOP INTERNAL PROCESSOR CLOCK, CLEAR I BIT IN CCR EXTERNAL Y RESET? N IRQ Y ...

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... SWAIT in the MOR) if the COP watchdog timer is required to function at all times. Furthermore recommended that the COP watchdog timer be disabled for applications that will use the wait mode for time periods that will exceed the COP timeout period. MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 30 NOTE Freescale Semiconductor ...

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... There is a 4064 internal clock cycle oscillator stabilization delay after the oscillator becomes active. MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor Figure 4-1. The CPU and all peripheral modules will be ...

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... When the reset condition ends, the MCU’s operating mode will be selected (see Table 3-1. Operating Mode Conditions After MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 32 –V ), the COP watchdog timer’s output will be restored if the COP Unimplemented Reset). pin is returned to its normal Bit COPR Freescale Semiconductor to DD ...

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... CPU state to be recovered from the stack and normal processing to resume at the next instruction that was to be executed when the interrupt took place. events that occurs during interrupt processing. MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor Table 5-1 will be serviced first. CPU ...

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... RTI INSTRUCTION? N EXECUTE INSTRUCTION Figure 5-1. Interrupt Processing Flowchart MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 34 CLEAR IRQ Y REQUEST LATCH Y STACK PC BIT IN CCR LOAD PC FROM: SWI: $1FFC, $1FFD IRQ: $1FFA-$1FFB TIMER: $1FF8-$1FF9 Y RESTORE RESISTERS Y FROM STACK CC SET Freescale Semiconductor ...

Page 35

... TCR. The I bit in the CCR must be clear for the input capture interrupt to be enabled. The interrupt service routine address is specified by the contents of memory locations $1FF8 and $1FF9. MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor Chapter 4 Resets. pin is ignored. The interrupt service routine address is PP pin ...

Page 36

... TCR. The I bit in the CCR must be clear for the timer overflow interrupt to be enabled. This internal interrupt will vector to the interrupt service routine located at the address specified by the contents of memory locations $1FF8 and $1FF9. MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 36 Chapter 8 Capture/Compare Chapter 8 Capture/Compare Freescale Semiconductor ...

Page 37

... WRITE $0004 RESET (RST) WRITE $0000 READ $0000 INTERNAL HC05 DATA BUS Figure 6-1. Port A I/O and Interrupt Circuitry MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor NOTE OPTION REGISTER DATA DIRECTION REGISTER BIT DATA REGISTER BIT V DD PULLUP MASK ...

Page 38

... DDR registers will produce unpredictable results in the A/D subsystem. See Subsystem. MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 38 Chapter 7 Serial Input/Output Port (SIOP) DATA DIRECTION REGISTER BIT DATA REGISTER BIT Figure 6-2. Port B I/O Circuitry for a discussion of the I/O OUTPUT PIN Chapter 9 Analog Freescale Semiconductor ...

Page 39

... A pin is configured as an output if its corresponding DDR bit is set to a logic 1. A pin is configured as an input if its corresponding DDR bit is cleared to a logic 0. MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor DATA DIRECTION REGISTER BIT DATA REGISTER BIT Figure 6-3 ...

Page 40

... Accesses to Data Register @ $0001 Read Write I/O Pin See Note PB5–PB7 PB5–PB7 Accesses to Data Register @ $0002 Read Write I/O Pin See Note PC0–PC7 PC0–PC7 Accesses to Data Register @ $0003 Read Write I/O Pin See Note 1 PD5 PD5 Freescale Semiconductor ...

Page 41

... HCO5 INTERNAL BUS BAUD CONTROL RATE REGISTER GENERATOR $0A INTERNAL CPU CLOCK MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor Figure 7-1. A mask programmable option determines whether the SIOP 8-BIT STATUS SHIFT REGISTER REGISTER $0B $0C Figure 7-1. SIOP Block Diagram ...

Page 42

... MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 42 for a description of available SCK frequencies. BIT 1 BIT 2 BIT 3 BIT 4 BIT 1 BIT 2 BIT 3 BIT 4 Figure 7-2. SIOP Timing Diagram for MOR LSBF programming information. Figure 7-2. BIT 5 BIT 6 BIT 7 100 ns BIT 5 BIT 6 BIT 7 Freescale Semiconductor ...

Page 43

... The MSTR bit is readable and writeable at any time regardless of the state of the SPE bit. Clearing the MSTR bit will abort any transfers that may have been in progress. Reset clears the MSTR bit as well as the SPE bit, disabling the SIOP subsystem. MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor ...

Page 44

... MC68HC705P6A Advance Information Data Sheet, Rev. 2 DCOL Figure 7-4. SIOP Status Register (SSR) shows the position of each bit in the register. This register is not SD6 SD5 SD4 SD3 Unaffected by reset Figure 7-4 shows the position of each bit 2 1 Bit Bit 0 SD2 SD1 SD0 Freescale Semiconductor ...

Page 45

... REGISTER OUTPUT COMPARE CIRCUIT TIMER STATUS ICF OCF TOF $13 REG. INTERRUPT CIRCUIT Figure 8-1. Capture/Compare Timer Block Diagram MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor INTERNAL BUS INTERNAL PROCESSOR 8-BIT CLOCK BUFFER ³³³ ÷4 HIGH LOW BYTE ...

Page 46

... Timer status register (TSR) • Timer registers (TRH and TRL) • Alternate timer registers (ATRH and ATRL) • Input capture registers (ICRH and ICRL) • Output compare registers (OCRH and OCRL) MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 46 Freescale Semiconductor ...

Page 47

... The state of this read/write bit determines whether a logic 1 or logic 0 appears on the TCMP pin when a successful output compare occurs. Resets clear the OLVL bit TCMP goes high on output compare 0 = TCMP goes low on output compare MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor Figure 8-2, performs these functions ...

Page 48

... TOF bit by reading the timer status register with TOF set, and then reading the low byte ($0019) of the timer registers. Resets have no effect on TOF. MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 48 Figure 8-3, contains flags to signal the following conditions OCF TOF Unimplemented U = Undetermined Figure 8-3. Timer Status Register (TSR Bit Freescale Semiconductor ...

Page 49

... To prevent interrupts from occurring between readings of ATRH and ATRL, set the interrupt flag in the condition code register before reading ATRH, and clear the flag after reading ATRL. MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor Figure 8-4, contains the current high and low bytes of the 6 ...

Page 50

... Figure 8-7. Output Compare Registers (OCRH and OCRL) MC68HC705P6A Advance Information Data Sheet, Rev. 2 ICRH6 ICRH5 ICRH4 ICRH3 Unaffected by reset Unaffected by reset = Unimplemented NOTE OCRH6 OCRH5 OCRH4 OCRH3 Unaffected by reset Unaffected by reset 2 1 Bit 0 ICRH2 ICRH1 ICRH0 2 1 Bit Bit 0 OCRH2 OCRH1 OCRH0 2 1 Bit 0 Freescale Semiconductor ...

Page 51

... If reset is used to exit stop mode, then no input capture flag or data remains, even if a valid input capture edge occurred. MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor Timer During Wait/Halt Mode 51 ...

Page 52

... Capture/Compare Timer MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 52 Freescale Semiconductor ...

Page 53

... Digital Section The following paragraphs describe the operation and performance of digital modules within the analog subsystem. MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor supplying the high reference voltage. Applying an input REFH should be at the same potential as the supply ...

Page 54

... ADC register will be updated with new data, and the CC bit set every 32 internal clock cycles. Also, data from the previous conversion will be overwritten regardless of the state of the CC bit. MC68HC705P6A Advance Information Data Sheet, Rev. 2 ADRC ADON Figure 9- Bit 0 CH2 CH1 CH0 Freescale Semiconductor ...

Page 55

... Bit 7 Read: AD7 Write: Reset: = Unimplemented Figure 9-2. A/D Conversion Value Data Register (ADC) MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor , to stabilize before accurate conversion results can be RCON for more information. Channel 0 AD0 — port C, bit 6 1 AD1 — port C, bit 5 2 AD2 — ...

Page 56

... A/D subsystem stabilizes sufficiently to provide conversions at its rated accuracy. The delays built into the MC68HC705P6A when coming out of stop mode are sufficient for this purpose. No explicit delays need to be added to the application software. MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 56 Freescale Semiconductor ...

Page 57

... This register is used to program the EPROM array. Only the ELAT and EPGM bits are available. Table 10-1 shows the location of each bit in the EPROG register and the state of these bits coming out of reset. All the bits in the EPROG register are cleared by reset. MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor NOTE Table 10-1. NOTE ...

Page 58

... Bit 0 0 ELAT EPGM EPGM 10-1. PROGRAMMING REG DATA VALUE A SAMPLE EPROM ADX EPGM BIT IN EPROG REG SET LAT BIT IN EPROG DATA BYTE WRITE IT TO EPROM LOC TURN ON PGM VOLTAGE WAIT 4 ms MINIMUM CLR LAT AND PGM BITS Freescale Semiconductor ...

Page 59

... When complete, close the RESET switch to force the MCU into the reset state. 11. Turn off the V source. PP 12. Turn off the V source. DD 13. Remove device(s). MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor Table 10-2. Bootloader Control Pins PC3 1 1 Program/verify ...

Page 60

... MC68HC705P6A Advance Information Data Sheet, Rev. 2 CLOSE PROGRAM SWITCH N CLOSE VERIFY SWITCH VERIFICATION FAILED N PROGRAMMING? Y WAIT FOR PROGRAMMING LED TO TURN ON AND OFF. N VERIFYING? Y WAIT FOR 30 SECONDS N IS VERIFY LED LIT? Y VERIFICATION COMPLETE CLOSE RESET SWITCH TURN OFF V PP TURN OFF V DD REMOVE DEVICES Freescale Semiconductor ...

Page 61

... V DD PC6 PROG PB7 330 Ω VERF PB6 330 Ω PC5 Figure 10-3. MC68HC705P6A EPROM Programming Schematic Diagram MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor Programming from an External Memory Device 2764 PD7/TCAP V DD PB5 A12 PA7 D7 PA6 D6 PA5 D5 PA4 ...

Page 62

... EPROM MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 62 Freescale Semiconductor ...

Page 63

... Setting the COP bit will enable the COP watchdog timer. The COP will reset the MCU if the timeout period is reached before the COP watchdog timer is cleared by the application software and the voltage applied to the IRQ/V watchdog timer regardless of the voltage applied to the IRQ/V MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor PA6PU ...

Page 64

... PP pin will be sensitive to both the falling edge of PP Table Table 11-1. SIOP Clock Rate SPR0 SIOP Master Clock osc osc osc osc NOTE pin. PP 11-1. ÷ 64 ÷ 32 ÷ 16 ÷ 8 Freescale Semiconductor ...

Page 65

... B7 1C 00E4 A6 FF 00E6 00E9 12 1C 00EB AD 03 00ED 3F 1C 00EF 81 MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor Flowchart. In order to allow programming, all the ). EPGM pin. PP Table Table 11-2. MOR Programming Routine EPROG EQU $1C DATA2 EQU $FF DATA1 EQU ...

Page 66

... Mask Option Register (MOR) MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 66 Freescale Semiconductor ...

Page 67

... Accumulator The accumulator is a general-purpose 8-bit register as shown in accumulator to hold operands and results of arithmetic calculations or non-arithmetic operations. The accumulator is unaffected by a reset of the device. MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor Figure 12-1 and are described in the following paragraphs ...

Page 68

... MC68HC705P6A Advance Information Data Sheet, Rev. 2 8-bit register that can perform two functions 16-bit register internally. In devices with memory maps less Figure 12 16-bit register internally. In devices with memory maps is a 5-bit register in which four bits are used to indicate the results of the Freescale Semiconductor ...

Page 69

... The carry/borrow bit is also set or cleared during bit test and branch instructions and during shifts and rotates. This bit is not set by an INC or DEC instruction. MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor Registers 69 ...

Page 70

... Central Processor Unit (CPU) Core MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 70 Freescale Semiconductor ...

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... Direct instructions can access any of the first 256 memory locations with two bytes. The first byte is the opcode, and the second is the low byte of the operand address. In direct addressing, the CPU automatically uses $00 as the high byte of the operand address. MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor 71 ...

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... When using the Freescale assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch. MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 72 Freescale Semiconductor ...

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... Multiply OR Accumulator with Memory Byte Subtract Memory Byte and Carry Bit from Accumulator Store Accumulator in Memory Store Index Register in Memory Subtract Memory Byte from Accumulator MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor Instruction Instruction Types Mnemonic ADC ADD AND ...

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... BSET use only direct addressing. 2. TST is an exception to the read-modify-write sequence because it does not write a replacement value. MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 74 NOTE Instruction Mnemonic ASL ASR BCLR BSET CLR COM DEC INC LSL LSR NEG ROL ROR TST (1) (1) (2) Freescale Semiconductor ...

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... Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always Branch if Bit Clear Branch Never Branch if Bit Set Branch to Subroutine Unconditional Jump Jump to Subroutine MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor Instruction Mnemonic BCC BCS BEQ BHCC BHCS BHI BHS BIH ...

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... Transfer Index Register to Accumulator Stop CPU Clock and Enable Interrupts MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 76 Instruction Table 13-5. Control Instructions Instruction Mnemonic BCLR BRCLR BRSET BSET Mnemonic CLC CLI NOP RSP RTI RTS SEC SEI STOP SWI TAX TXA WAIT Freescale Semiconductor ...

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... BHCC rel Branch if Half-Carry Bit Clear BHCS rel Branch if Half-Carry Bit Set BHI rel Branch if Higher BHS rel Branch if Higher or Same MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor Effect on CCR Description ← (A) + (M) + (C) — A ← (A) + (M) — A ← (A) ∧ (M) — ...

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... F5 3 REL REL REL REL REL REL REL REL DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 REL DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 REL INH 98 2 INH 9A 2 Freescale Semiconductor ...

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... JMP opr,X Unconditional Jump JMP opr,X JMP ,X JSR opr JSR opr JSR opr,X Jump to Subroutine JSR opr,X JSR ,X MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor Effect on CCR Description ← $00 A ← $00 X ← $00 — — — M ← $00 M ← $00 (A) – ...

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... DIR 34 5 INH 44 3 INH 54 3 IX1 INH DIR 30 5 INH 40 3 INH 50 3 IX1 INH IMM DIR EXT CA 4 — IX2 IX1 DIR 39 5 INH 49 3 INH 59 3 IX1 DIR 36 5 INH 46 3 INH 56 3 IX1 INH 9C 2 Freescale Semiconductor ...

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... Transfer Accumulator to Index Register TST opr TSTA TSTX Test Memory Byte for Negative or Zero TST opr,X TST ,X MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor Effect on CCR Description ← (SP Pull (CCR) SP ← (SP Pull (A) SP ← (SP Pull (X) SP ← (SP Pull (PCH) SP ← ...

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... Relative program counter offset byte SP Stack pointer X Index register Z Zero flag # Immediate value ∧ Logical AND ∨ Logical OR ⊕ Logical EXCLUSIVE Contents of –( ) Negation (two’s complement) ← Loaded with ? If : Concatenated with Set or cleared — Not affected Freescale Semiconductor INH 9F 2 INH 8F 2 ...

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Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA 3 DIR 2 DIR 2 REL 2 DIR BRCLR0 ...

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... Instruction Set MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 84 Freescale Semiconductor ...

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... DC Electrical Characteristics 14.6 3.3-Volt DC Electrical Charactertistics conditions. 14.3 Operating Temperature Range Characteristic Operating temperature range MC68HC705P6A (standard) MC68HC705P6AC (extended) 14.4 Thermal Characteristics Characteristic Thermal resistance PDIP SOIC MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor Symbol and stg NOTE ...

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... MHz), all inputs 0.2 V osc Freescale Semiconductor Unit µA µA µA µA µA µA µA pF ...

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... To be measured using external square wave clock source ( from rail loads, less than all outputs Wait, Stop I : All ports configured as inputs Wait I will be affected linearly by the OSC2 capacitance Stop measured with OSC1 = V DD MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor (1) Symbol RESET ...

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... Unit Comments Bits LSB Including quanitization A/D accuracy may decrease proportionately REFH reduced below 4.0 µA t Includes sampling time cyc µ Hex Hex in REFH t cyc µ µs t ADON µ Min Typ Max 16.25 16.5 16.75 — 5 — — Freescale Semiconductor Unit ...

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... SDO data valid time 4 SDO hold time 5 SDI setup time 6 SDI hold time SCK SDI t 3 SDO MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor Symbol t 1 BIT 0 BIT 1 ... BIT 0 BIT 1 ... 6 Figure 14-1. SIOP Timing Diagram SIOP Timing Min ...

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... A Symbol Min Max f — 4.2 OSC DC 4.2 f — 2 2.1 t 476 — CYC t — 100 OXOV t — 100 ILCH t 1.5 — 125 — ILIH t Note 2 — ILIL 200 — 100 ADON Freescale Semiconductor Unit MHz MHz CYC ns t CYC ns µs ...

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VDDR V THRESHOLD (1-2 V TYPICAL (2) OSC1 4064 t cyc t cyc INTERNAL PROCESSOR (1) CLOCK INTERNAL ADDRESS 1FFE 1FFF NEW PC BUS (1) INTERNAL NEW NEW DATA PCH PCL (1) BUS RESET Notes: 1. ...

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... Electrical Specifications MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 92 Freescale Semiconductor ...

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... Chapter 15 Mechanical Specifications 15.1 Introduction The MC68HC705P6A is available in either a 28-pin plastic dual in-line (PDIP 28-pin small outline integrated circuit (SOIC) package. 15.2 Plastic Dual In-Line Package (Case 710 MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor SEATING PLANE NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0 ...

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... F 0.41 0.90 0.016 F G 1.27 BSC 0.050 BSC J 0.23 0.32 0.009 J K 0.13 0.29 0.005 M 0° 8° 0° P 10.05 10.55 0.395 R 0.25 0.75 0.010 Freescale Semiconductor MAX 0.711 0.299 0.104 0.019 0.035 0.013 0.011 8° 0.415 0.029 ...

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... The following table shows the MC order numbers for the available package types. MC Order Number MC68HC705P6ACP MC68HC705P6ACDW Plastic dual in-line package Small outline integrated circuit (SOIC) package MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 Freescale Semiconductor (1) (extended) (2) (extended) Operating Temperature Range ° ...

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... Ordering Information MC68HC705P6A Advance Information Data Sheet, Rev. 2.1 96 Freescale Semiconductor ...

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...

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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...

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