MC705P6ACDWE Freescale Semiconductor, MC705P6ACDWE Datasheet - Page 39

IC MCU 176 BYTES RAM 28-SOIC

MC705P6ACDWE

Manufacturer Part Number
MC705P6ACDWE
Description
IC MCU 176 BYTES RAM 28-SOIC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC705P6ACDWE

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SIO
Peripherals
POR, WDT
Number Of I /o
21
Program Memory Size
4.5KB (4.5K x 8)
Program Memory Type
OTP
Ram Size
176 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
HC705P
Core
HC05
Data Bus Width
8 bit
Data Ram Size
176 B
Maximum Clock Frequency
2.1 MHz
Number Of Programmable I/os
21
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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0
6.5 Port D
Port D is a 2-bit port with one bidirectional pin (PD5) and one input-only pin (PD7). Pin PD7 is shared with
the 16-bit timer. The port D data register is located at address $0003 and its data direction register (DDR)
is located at address $0007. The contents of the port D data register are indeterminate at initial powerup
and must be initialized by user software. Reset does not affect the data registers, but clears the DDRs,
thereby setting PD5 to input mode. Writing a 1 to DDR bit 5 sets PD5 to output mode (see
Port D may be used for general I/O applications regardless of the state of the 16-bit timer. Since PD7 is
an input-only line, its state can be read from the port D data register at any time.
6.6 I/O Port Programming
Each pin on port A through port D (except pin 7 of port D) can be programmed as an input or an output
under software control as shown in
is determined by the state of its corresponding bit in the associated port data direction register (DDR). A
pin is configured as an output if its corresponding DDR bit is set to a logic 1. A pin is configured as an
input if its corresponding DDR bit is cleared to a logic 0.
Freescale Semiconductor
INTERNAL HC05
INTERNAL HC05
DATA BUS
DATA BUS
WRITE $0006
WRITE $0002
READ $0006
READ $0002
WRITE $0007
WRITE $0003
READ $0007
READ $0003
RESET
RESET
(RST)
(RST)
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
DATA DIRECTION
DATA DIRECTION
Table
Figure 6-3. Port C I/O Circuitry
Figure 6-4. Port D I/O Circuitry
REGISTER BIT
REGISTER BIT
REGISTER BIT
REGISTER BIT
DATA
DATA
6-1,
Table
6-2,
Table
6-3, and
Table
6-4. The direction of a pin
OUTPUT
OUTPUT
Figure
PIN
PIN
I/O
I/O
6-4).
Port D
39