ATMEGA8A-MUR Atmel, ATMEGA8A-MUR Datasheet - Page 157
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ATMEGA8A-MUR
Manufacturer Part Number
ATMEGA8A-MUR
Description
MCU AVR 8KB FLASH 16MHZ 32QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA8A-MU.pdf
(308 pages)
Specifications of ATMEGA8A-MUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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19.10.2
8159D–AVR–02/11
UCSRA – USART Control and Status Register A
• Bit 7 – RXC: USART Receive Complete
This flag bit is set when there are unread data in the receive buffer and cleared when the receive
buffer is empty (i.e. does not contain any unread data). If the Receiver is disabled, the receive
buffer will be flushed and consequently the RXC bit will become zero. The RXC Flag can be
used to generate a Receive Complete interrupt (see description of the RXCIE bit).
• Bit 6 – TXC: USART Transmit Complete
This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and
there are no new data currently present in the transmit buffer (UDR). The TXC Flag bit is auto-
matically cleared when a transmit complete interrupt is executed, or it can be cleared by writing
a one to its bit location. The TXC Flag can generate a Transmit Complete interrupt (see descrip-
tion of the TXCIE bit).
• Bit 5 – UDRE: USART Data Register Empty
The UDRE Flag indicates if the transmit buffer (UDR) is ready to receive new data. If UDRE is
one, the buffer is empty, and therefore ready to be written. The UDRE Flag can generate a Data
Register Empty interrupt (see description of the UDRIE bit).
UDRE is set after a reset to indicate that the Transmitter is ready.
• Bit 4 – FE: Frame Error
This bit is set if the next character in the receive buffer had a Frame Error when received (i.e.,
when the first stop bit of the next character in the receive buffer is zero). This bit is valid until the
receive buffer (UDR) is read. The FE bit is zero when the stop bit of received data is one. Always
set this bit to zero when writing to UCSRA.
• Bit 3 – DOR: Data OverRun
This bit is set if a Data OverRun condition is detected. A Data OverRun occurs when the receive
buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a
new start bit is detected. This bit is valid until the receive buffer (UDR) is read. Always set this bit
to zero when writing to UCSRA.
• Bit 2 – PE: Parity Error
This bit is set if the next character in the receive buffer had a Parity Error when received and the
parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer
(UDR) is read. Always set this bit to zero when writing to UCSRA.
• Bit 1 – U2X: Double the USART transmission speed
This bit only has effect for the asynchronous operation. Write this bit to zero when using syn-
chronous operation.
Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively dou-
bling the transfer rate for asynchronous communication.
Bit
Read/Write
Initial Value
RXC
R
7
0
TXC
R/W
6
0
UDRE
R
5
1
FE
R
4
0
DOR
R
3
0
PE
R
2
0
U2X
R/W
1
0
ATmega8A
MPCM
R/W
0
0
UCSRA
157
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