ATMEGA8A-MUR Atmel, ATMEGA8A-MUR Datasheet - Page 19
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ATMEGA8A-MUR
Manufacturer Part Number
ATMEGA8A-MUR
Description
MCU AVR 8KB FLASH 16MHZ 32QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA8A-MU.pdf
(308 pages)
Specifications of ATMEGA8A-MUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 19 of 308
- Download datasheet (6Mb)
7.6
7.6.1
7.6.2
7.6.3
8159D–AVR–02/11
Register Description
EEARH and EEARL – The EEPROM Address Register
EEDR – The EEPROM Data Register
EECR – The EEPROM Control Register
• Bits 15:9 – Res: Reserved Bits
These bits are reserved bits in the ATmega8A and will always read as zero.
• Bits 8:0 – EEAR8:0: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL – specify the EEPROM address in the
512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and
511. The initial value of EEAR is undefined. A proper value must be written before the EEPROM
may be accessed.
• Bits 7:0 – EEDR7:0: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEAR.
• Bits 7:4 – Res: Reserved Bits
These bits are reserved bits in the ATmega8A and will always read as zero.
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing
EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant inter-
rupt when EEWE is cleared.
• Bit 2 – EEMWE: EEPROM Master Write Enable
The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written.
When EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM at
the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
EEAR7
MSB
R/W
R/W
15
R
X
R
–
7
0
7
0
7
–
0
EEAR6
R/W
R/W
14
R
X
R
–
6
0
6
0
6
–
0
EEAR5
R/W
R/W
13
R
X
R
–
5
0
5
0
5
–
0
EEAR4
R/W
R/W
12
R
R
–
4
0
X
4
0
4
0
–
EEAR3
EERIE
R/W
R/W
R/W
11
R
X
–
3
0
3
0
3
0
EEMWE
EEAR2
R/W
R/W
R/W
10
R
X
–
2
0
2
0
2
0
EEAR1
EEWE
R/W
R/W
R/W
R
X
X
9
–
1
0
1
0
1
ATmega8A
EEAR8
EEAR0
EERE
R/W
R/W
LSB
R/W
R/W
8
0
X
X
0
0
0
0
EEARH
EEARL
EEDR
EECR
19
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