ATMEGA8A-MUR Atmel, ATMEGA8A-MUR Datasheet - Page 97

• Manufacturer Part Number: ATMEGA8A-MUR
• Description: MCU AVR 8KB FLASH 16MHZ 32QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8A-MUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.10 Timer/Counter Timing Diagrams
8159D–AVR–02/11
port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing)
the OC1x Register at the Compare Match between OCR1x and TCNT1 when the counter incre-
ments, and clearing (or setting) the OC1x Register at Compare Match between OCR1x and
TCNT1 when the counter decrements. The PWM frequency for the output when using phase
and frequency correct PWM can be calculated by the following equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1x Register represents special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the
output will be continuously low and if set equal to TOP the output will be set to high for non-
inverted PWM mode. For inverted PWM the output will have the opposite logic values.
If OCR1A is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A output
will toggle with a 50% duty cycle.
The Timer/Counter is a synchronous design and the timer clock (clk
clock enable signal in the following figures. The figures include information on when Interrupt
Flags are set, and when the OCR1x Register is updated with the OCR1x buffer value (only for
modes utilizing double buffering).
Figure 16-10. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling
Figure 16-11
TCNTn
OCRnx
OCFnx
(clk
clk
clk
I/O
I/O
Tn
/1)
shows the same timing data, but with the prescaler enabled.
OCRnx - 1
f
OCnxPFCPWM
Figure 16-10
OCRnx
shows a timing diagram for the setting of OCF1x.
OCRnx Value
=
--------------------------- -
2 N TOP
⋅
f
clk_I/O
⋅
OCRnx + 1
T1
) is therefore shown as a
ATmega8A
OCRnx + 2
97