ATXMEGA16A4-CUR Atmel, ATXMEGA16A4-CUR Datasheet - Page 249

• Manufacturer Part Number: ATXMEGA16A4-CUR
• Description: MCU AVR 16+4KB FLASH 49VFBGA
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA16A4-CUR

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 49-VFBGA
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.13 IRCOM Mode of Operation
21.14 DMA Support
21.15 Register Description
21.15.1
21.15.2
8077H–AVR–12/09
DATA - USART I/O Data Register
STATUS - USART Status Register
IRCOM mode can be enabled to use the IRCOM Module with the USART. This enables IrDA 1.4
physical compliant modulation and demodulation for baud rates up to 115.2 Kbps. When IRCOM
mode is enabled, Double Transmission Speed cannot be used for the USART.
For devices with more than one USART, IRCOM mode can only be enabled for one USART at a
time. For details refer to
DMA support is available on the UART, USRT and SPI Master mode peripherals. For details on
different USART DMA transfer triggers refer to
The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the
same I/O address referred to as USART Data Register (DATA). The Transmit Data Buffer Reg-
ister (TXB) will be the destination for data written to the DATA Register location. Reading the
DATA Register location will return the contents of the Receive Data Buffer Register (RXB).
For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to
zero by the Receiver.
The transmit buffer can only be written when the DREIF Flag in the STATUS Register is set.
Data written to DATA when the DREIF Flag is not set, will be ignored by the USART Transmitter.
When data is written to the transmit buffer, and the Transmitter is enabled, the Transmitter will
load the data into the Transmit Shift Register when the Shift Register is empty. The data is then
transmitted on the TxD pin.
The receive buffer consists of a two level FIFO. The FIFO and the corresponding flags in the
Status Register (STATUS) will change state whenever the receive buffer is accessed (read).
Always read STATUS before DATA in order to get the correct flags.
• Bit 7 - RXCIF: USART Receive Complete Interrupt Flag
This flag is set when there are unread data in the receive buffer and cleared when the receive
buffer is empty (i.e., does not contain any unread data). When the Receiver is disabled, the
receive buffer will be flushed and consequently the RXCIF will become zero.
Bit
+0x00
Read/Write
Initial Value
Bit
+0x01
Read/Write
Initial Value
RXCIF
R
7
0
R/W
7
0
TXCIF
R/W
6
0
Section 22. ”IRCOM - IR Communication Module” on page
R/W
6
0
DREIF
R
5
1
R/W
5
0
FERR
R
4
0
R/W
Section 5.4 ”Transfer Triggers” on page
4
0
RXB[[7:0]
BUFOVF
TXB[[7:0]
R
3
0
R/W
3
0
PERR
R
2
0
R/W
2
0
1
R
0
-
XMEGA A
R/W
1
0
RXB8
R/W
0
0
256.
50.
STATUS
R/W
0
0
249