ATMEGA32U4-AUR Atmel, ATMEGA32U4-AUR Datasheet - Page 220
![MCU AVR 16K FLASH 16MHZ 44TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
ATMEGA32U4-AUR
Manufacturer Part Number
ATMEGA32U4-AUR
Description
MCU AVR 16K FLASH 16MHZ 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA16U4-MU.pdf
(433 pages)
Specifications of ATMEGA32U4-AUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
26
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Manufacturer
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Price
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19.6.3
19.6.4
7766F–AVR–11/10
USART MSPIM Control and Status Register n B - UCSRnB
USART MSPIM Control and Status Register n C - UCSRnC
• Bit 7 - RXCIEn: RX Complete Interrupt Enable
Writing this bit to one enables interrupt on the RXCn Flag. A USART Receive Complete interrupt
will be generated only if the RXCIEn bit is written to one, the Global Interrupt Flag in SREG is
written to one and the RXCn bit in UCSRnA is set.
• Bit 6 - TXCIEn: TX Complete Interrupt Enable
Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete interrupt
will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG is
written to one and the TXCn bit in UCSRnA is set.
• Bit 5 - UDRIE: USART Data Register Empty Interrupt Enable
Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will
be generated only if the UDRIE bit is written to one, the Global Interrupt Flag in SREG is written
to one and the UDREn bit in UCSRnA is set.
• Bit 4 - RXENn: Receiver Enable
Writing this bit to one enables the USART Receiver in MSPIM mode. The Receiver will override
normal port operation for the RxDn pin when enabled. Disabling the Receiver will flush the
receive buffer. Only enabling the receiver in MSPI mode (i.e. setting RXENn=1 and TXENn=0)
has no meaning since it is the transmitter that controls the transfer clock and since only master
mode is supported.
• Bit 3 - TXENn: Transmitter Enable
Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port
operation for the TxDn pin when enabled. The disabling of the Transmitter (writing TXENn to
zero) will not become effective until ongoing and pending transmissions are completed, i.e.,
when the Transmit Shift Register and Transmit Buffer Register do not contain data to be trans-
mitted. When disabled, the Transmitter will no longer override the TxDn port.
• Bit 2:0 - Reserved Bits in MSPI mode
When in MSPI mode, these bits are reserved for future use. For compatibility with future devices,
these bits must be written to zero when UCSRnB is written.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
7
UMSELn1
R/W
0
7
RXCIEn
R/W
0
6
UMSELn0
R/W
0
6
TXCIEn
R/W
0
5
UDRIE
R/W
0
5
-
R
0
4
-
R
0
4
RXENn
R/W
0
3
-
R
0
3
TXENn
R/W
0
2
UDORDn
R/W
1
2
-
R
1
1
UCPHAn
R/W
1
ATmega16/32U4
1
-
R
1
0
UCPOLn
R/W
0
0
-
R
0
UCSRnB
UCSRnC
220
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