AT90PWM3B-16MU Atmel, AT90PWM3B-16MU Datasheet - Page 218
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AT90PWM3B-16MU
Manufacturer Part Number
AT90PWM3B-16MU
Description
IC MCU AVR RISC 8K FLASH 32-QFN
Manufacturer
Atmel
Series
AVR® 90PWM Lightingr
Datasheet
1.AT90PWM3B-16SU.pdf
(361 pages)
Specifications of AT90PWM3B-16MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
27
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
32-QFN
Package
32QFN EP
Device Core
AVR
Family Name
90P
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
27
Interface Type
SPI/USART
On-chip Adc
11-chx10-bit
Number Of Timers
2
Processor Series
AT90PWMx
Core
AVR8
Data Ram Size
512 B
Maximum Clock Frequency
16 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRFBKIT, ATAVRISP2
Minimum Operating Temperature
- 40 C
On-chip Dac
10 bit, 1 Channel
For Use With
ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRMC200 - KIT EVAL FOR AT90PWM3 ASYNCATAVRFBKIT - KIT DEMO BALLAST FOR AT90PWM2ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK520 - ADAPTER KIT FOR 90PWM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT90PWM3B-16MU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
AT90PWM3B-16MUR
Manufacturer:
TI
Quantity:
1 829
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19.4.4
19.4.5
19.4.6
19.4.7
19.5
19.5.1
19.5.2
218
Data Reception – EUSART Receiver
AT90PWM2/3/2B/3B
Sending 17 Data Bit Frames
Transmitter Flags and Interrupts
Disabling the Transmitter
Data Reception – EUSART Receiver
Receiving Frames with 5 to 8 Data Bits
Receiving Frames with 9, 13, 14, 15 or 16 Data Bits
In this configuration the seventeenth bit shoud be loaded in the RXB8 bit register, the rest of the
most significant bits (9, 10, 11, 12, 13, 14, 15 and 16) should be loaded in the EUDR register,
before the low byte of the character is written to UDR.
The behavior of the EUSART is the same as in USART mode (See “Receive Complete Flag and
Interrupt”).
The interrupts generation and handling for transmission in EUSART mode are the same as in
USART mode.
The disabling of the Transmitter (setting the TXEN to zero) will not become effective until ongo-
ing and pending transmissions are completed, i.e., when the Transmit Shift Register and
Transmit Buffer Register do not contain data to be transmitted.
The EUSART Receiver is enabled by writing the Receive Enable (RXEN) bit in the UCSRB Reg-
ister to one (same as USART). When the Receiver is enabled, the normal pin operation of the
RxD pin is overridden by the EUSART and given the function as the Receiver’s serial input. The
baud rate, mode of operation and frame format must be set up once before any serial reception
can be done. If synchronous operation is used, the clock on the XCK pin will be used as transfer
clock.
In this mode the behavior is the same as the standard USART (See “Receiving Frames with 5 to
8 Data Bits” in USART section).
In these configurations the most significant bits (9, 13, 14, 15 or 16) should be read in the EUDR
register before reading the of the character in the UDR register.
Read status from EUCSRC, then data from UDR.
4317J–AVR–08/10
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