AT90PWM3B-16MU Atmel, AT90PWM3B-16MU Datasheet - Page 281

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AT90PWM3B-16MU

Manufacturer Part Number
AT90PWM3B-16MU
Description
IC MCU AVR RISC 8K FLASH 32-QFN
Manufacturer
Atmel
Series
AVR® 90PWM Lightingr
Datasheet

Specifications of AT90PWM3B-16MU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
27
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
32-QFN
Package
32QFN EP
Device Core
AVR
Family Name
90P
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
27
Interface Type
SPI/USART
On-chip Adc
11-chx10-bit
Number Of Timers
2
Processor Series
AT90PWMx
Core
AVR8
Data Ram Size
512 B
Maximum Clock Frequency
16 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRFBKIT, ATAVRISP2
Minimum Operating Temperature
- 40 C
On-chip Dac
10 bit, 1 Channel
For Use With
ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRMC200 - KIT EVAL FOR AT90PWM3 ASYNCATAVRFBKIT - KIT DEMO BALLAST FOR AT90PWM2ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK520 - ADAPTER KIT FOR 90PWM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT90PWM3B-16MU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
AT90PWM3B-16MUR
Manufacturer:
TI
Quantity:
1 829
25.3.1
4317J–AVR–08/10
Latching of Fuses
Table 25-5.
Notes:
Table 25-6.
Note:
The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if
Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the Lock bits.
The fuse values are latched when the device enters programming mode and changes of the
fuse values will have no effect until the part leaves Programming mode. This does not apply to
the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on
Power-up in Normal mode.
High Fuse Byte
RSTDISBL
DWEN
SPIEN
WDTON
EESAVE
BODLEVEL2
BODLEVEL1
BODLEVEL0
Low Fuse Byte
CKDIV8
CKOUT
SUT1
SUT0
CKSEL3
CKSEL2
CKSEL1
CKSEL0
(2)
1. See
2. The SPIEN Fuse is not accessible in serial programming mode.
3. See
4. See
1. The default value of SUT1..0 results in maximum start-up time for the default clock source.
2. The default setting of CKSEL3..0 results in internal RC Oscillator @ 8 MHz. See
3. The CKOUT Fuse allows the system clock to be output on PORTB0. See
4. See
(3)
(4)
(3)
(1)
See
page 37
on page 37
(4)
(4)
(4)
Fuse High Byte
Fuse Low Byte
“Alternate Functions of Port C” on page 70
“Watchdog Timer Configuration” on page 54
Table 9-2 on page 48
Table 7-11 on page 37
“System Clock Prescaler” on page 37
for details.
for details.
Bit No
Bit No
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
for BODLEVEL Fuse decoding.
for details.
Description
External Reset Disable
debugWIRE Enable
Enable Serial Program and
Data Downloading
Watchdog Timer Always On
EEPROM memory is
preserved through the Chip
Erase
Brown-out Detector trigger
level
Brown-out Detector trigger
level
Brown-out Detector trigger
level
Description
Divide clock by 8
Clock output
Select start-up time
Select start-up time
Select Clock source
Select Clock source
Select Clock source
Select Clock source
for details.
for description of RSTDISBL Fuse.
for details.
AT90PWM2/3/2B/3B
1 (unprogrammed)
1 (unprogrammed)
Default Value
0 (programmed)
1 (unprogrammed)
0 (programmed)
0 (programmed)
0 (programmed)
1 (unprogrammed)
0 (programmed)
Default Value
1 (unprogrammed)
0 (programmed, SPI
programming enabled)
1 (unprogrammed), EEPROM
not reserved
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
“Clock Output Buffer”
(1)
(2)
(2)
(2)
Table 7-11 on
(1)
(2)
281

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